mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
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Totoo
94 lines
2.8 KiB
C++
94 lines
2.8 KiB
C++
#ifndef __PROC_TETRA_H__
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#define __PROC_TETRA_H__
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#include "baseband_processor.hpp"
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#include "baseband_thread.hpp"
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#include "message.hpp"
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#include "dsp_decimate.hpp"
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#include "dsp_fir_taps.hpp"
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#include "rssi_thread.hpp"
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#include <cstdint>
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#include <array>
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#include <memory>
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class TetraProcessor : public BasebandProcessor {
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public:
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TetraProcessor();
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void execute(const buffer_c8_t& buffer) override;
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void on_message(const Message* const msg);
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private:
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static constexpr size_t baseband_fs = 3072000;
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static constexpr size_t channel_fs = 48000;
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static constexpr uint32_t symbol_rate = 18000;
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std::array<complex16_t, 512> dst_0{};
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const buffer_c16_t dst_buffer_0{dst_0.data(), dst_0.size()};
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std::array<complex16_t, 512> dst_1{};
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const buffer_c16_t dst_buffer_1{dst_1.data(), dst_1.size()};
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dsp::decimate::FIRC8xR16x24FS4Decim8 decim_0{};
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dsp::decimate::FIRC16xR16x32Decim8 decim_1{};
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// PLL and Timing
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uint32_t symbol_phase{0};
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uint32_t symbol_phase_inc{(uint32_t)((symbol_rate * 4294967296.0) / channel_fs)};
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complex16_t prompt_sample{0, 0};
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complex16_t prev_prompt{0, 0};
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complex16_t mid_sample{0, 0};
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complex16_t delay_sample{0, 0};
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static constexpr uint32_t BURST_BITS = 500;
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static constexpr uint32_t Y_SYNC_BITS = 38;
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static constexpr uint32_t SYNC_OFFSET = 214;
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static constexpr uint64_t Y_SYNC = 0x30673A7067ULL;
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static constexpr uint32_t DNB_TRAIN_BITS = 22;
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static constexpr uint32_t DNB_BLK_BITS = 216;
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static constexpr uint32_t DNB_TRAIN_TO_BLK2 = 22;
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static constexpr uint32_t DNB_TOTAL_T5_BITS = DNB_BLK_BITS * 2;
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static constexpr uint32_t N_SYNC = 0x343A74UL;
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static constexpr uint32_t P_SYNC = 0x1E90DEUL;
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static constexpr bool ENABLE_DNB_MESSAGES = true;
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uint32_t pll_phase{0};
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int32_t pll_freq{0};
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static constexpr int32_t pll_alpha = 150;
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static constexpr int32_t pll_beta = 2;
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uint64_t sync_register{0};
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std::array<uint8_t, 128> bit_history_buffer{};
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size_t history_write_idx{0};
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uint64_t bit_count{0};
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bool configured{false};
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struct PendingDnb {
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bool valid{false};
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uint64_t block1_start{0};
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uint64_t block2_start{0};
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uint64_t ready_at{0};
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bool inverted{false};
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bool p_train{false};
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uint8_t errors{0};
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} pending_dnb{};
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struct PendingDsb {
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bool valid{false};
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uint64_t burst_start{0};
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uint64_t ready_at{0};
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bool inverted{false};
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uint8_t errors{0};
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} pending_dsb{};
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void process_symbol(const complex16_t& sample);
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uint8_t history_bit(uint64_t absolute_bit) const;
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void push_burst_to_ui();
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void push_dnb_to_ui();
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BasebandThread baseband_thread{baseband_fs, this, baseband::Direction::Receive, false};
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RSSIThread rssi_thread{};
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};
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#endif // __PROC_TETRA_H__
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