mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-09-11 00:59:28 +00:00
ChibiOS 2.6.8, until I can figure out where to get it from git.
This commit is contained in:
Jared Boone
+261
@@ -0,0 +1,261 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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||||
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Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
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||||
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/**
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* @file STM32/GPIOv2/pal_lld.c
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* @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver code.
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*
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* @addtogroup PAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#if defined(STM32L1XX)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
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#define AHB_LPEN_MASK AHB_EN_MASK
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#elif defined(STM32F030) || defined(STM32F0XX_MD)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F0XX_LD)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F2XX)
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN)
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#elif defined(STM32F30X) || defined(STM32F37X)
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F4XX)
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#if STM32_HAS_GPIOF && STM32_HAS_GPIOG && STM32_HAS_GPIOI
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN)
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#else
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN)
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#endif /* STM32_HAS_GPIOF && STM32_HAS_GPIOG && STM32_HAS_GPIOI */
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#else
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#error "missing or unsupported platform for GPIOv2 PAL driver"
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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static void initgpio(GPIO_TypeDef *gpiop, const stm32_gpio_setup_t *config) {
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gpiop->OTYPER = config->otyper;
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gpiop->OSPEEDR = config->ospeedr;
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gpiop->PUPDR = config->pupdr;
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gpiop->ODR = config->odr;
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gpiop->AFRL = config->afrl;
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gpiop->AFRH = config->afrh;
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gpiop->MODER = config->moder;
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief STM32 I/O ports configuration.
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* @details Ports A-D(E, F, G, H) clocks enabled.
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*
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* @param[in] config the STM32 ports configuration
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*
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* @notapi
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*/
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void _pal_lld_init(const PALConfig *config) {
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/*
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* Enables the GPIO related clocks.
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*/
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#if defined(STM32L1XX)
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rccEnableAHB(AHB_EN_MASK, TRUE);
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RCC->AHBLPENR |= AHB_LPEN_MASK;
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#elif defined(STM32F0XX)
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rccEnableAHB(AHB_EN_MASK, TRUE);
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#elif defined(STM32F30X) || defined(STM32F37X)
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rccEnableAHB(AHB_EN_MASK, TRUE);
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#elif defined(STM32F2XX) || defined(STM32F4XX)
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RCC->AHB1ENR |= AHB1_EN_MASK;
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RCC->AHB1LPENR |= AHB1_LPEN_MASK;
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#endif
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/*
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* Initial GPIO setup.
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*/
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#if STM32_HAS_GPIOA
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initgpio(GPIOA, &config->PAData);
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#endif
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#if STM32_HAS_GPIOB
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initgpio(GPIOB, &config->PBData);
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#endif
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#if STM32_HAS_GPIOC
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initgpio(GPIOC, &config->PCData);
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#endif
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#if STM32_HAS_GPIOD
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initgpio(GPIOD, &config->PDData);
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#endif
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#if STM32_HAS_GPIOE
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initgpio(GPIOE, &config->PEData);
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#endif
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#if STM32_HAS_GPIOF
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initgpio(GPIOF, &config->PFData);
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#endif
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#if STM32_HAS_GPIOG
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initgpio(GPIOG, &config->PGData);
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#endif
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#if STM32_HAS_GPIOH
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initgpio(GPIOH, &config->PHData);
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#endif
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#if STM32_HAS_GPIOI
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initgpio(GPIOI, &config->PIData);
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#endif
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}
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/**
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* @brief Pads mode setup.
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* @details This function programs a pads group belonging to the same port
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* with the specified mode.
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* @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum
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* speed.
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*
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* @param[in] port the port identifier
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* @param[in] mask the group mask
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* @param[in] mode the mode
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*
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* @notapi
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*/
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#if 1
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode) {
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uint32_t moder = (mode & PAL_STM32_MODE_MASK) >> 0;
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uint32_t otyper = (mode & PAL_STM32_OTYPE_MASK) >> 2;
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uint32_t ospeedr = (mode & PAL_STM32_OSPEED_MASK) >> 3;
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uint32_t pupdr = (mode & PAL_STM32_PUDR_MASK) >> 5;
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uint32_t altr = (mode & PAL_STM32_ALTERNATE_MASK) >> 7;
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uint32_t bit = 0;
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while (TRUE) {
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if ((mask & 1) != 0) {
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uint32_t altrmask, m1, m2, m4;
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altrmask = altr << ((bit & 7) * 4);
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m4 = 15 << ((bit & 7) * 4);
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if (bit < 8)
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port->AFRL = (port->AFRL & ~m4) | altrmask;
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else
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port->AFRH = (port->AFRH & ~m4) | altrmask;
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m1 = 1 << bit;
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port->OTYPER = (port->OTYPER & ~m1) | otyper;
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m2 = 3 << (bit * 2);
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port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr;
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port->PUPDR = (port->PUPDR & ~m2) | pupdr;
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port->MODER = (port->MODER & ~m2) | moder;
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}
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mask >>= 1;
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if (!mask)
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return;
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otyper <<= 1;
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ospeedr <<= 2;
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pupdr <<= 2;
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moder <<= 2;
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bit++;
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}
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}
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#else
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode) {
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uint32_t afrm, moderm, pupdrm, otyperm, ospeedrm;
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uint32_t m1 = (uint32_t)mask;
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uint32_t m2 = 0;
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uint32_t m4l = 0;
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uint32_t m4h = 0;
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uint32_t bit = 0;
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do {
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if ((mask & 1) != 0) {
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m2 |= 3 << bit;
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if (bit < 16)
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m4l |= 15 << ((bit & 14) * 2);
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else
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m4h |= 15 << ((bit & 14) * 2);
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}
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bit += 2;
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mask >>= 1;
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} while (mask);
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afrm = ((mode & PAL_STM32_ALTERNATE_MASK) >> 7) * 0x1111;
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port->AFRL = (port->AFRL & ~m4l) | (afrm & m4l);
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port->AFRH = (port->AFRH & ~m4h) | (afrm & m4h);
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ospeedrm = ((mode & PAL_STM32_OSPEED_MASK) >> 3) * 0x5555;
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port->OSPEEDR = (port->OSPEEDR & ~m2) | (ospeedrm & m2);
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otyperm = ((mode & PAL_STM32_OTYPE_MASK) >> 2) * 0xffff;
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port->OTYPER = (port->OTYPER & ~m1) | (otyperm & m1);
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pupdrm = ((mode & PAL_STM32_PUDR_MASK) >> 5) * 0x5555;
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port->PUPDR = (port->PUPDR & ~m2) | (pupdrm & m2);
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moderm = ((mode & PAL_STM32_MODE_MASK) >> 0) * 0x5555;
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port->MODER = (port->MODER & ~m2) | (moderm & m2);
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}
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#endif
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#endif /* HAL_USE_PAL */
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/** @} */
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+461
@@ -0,0 +1,461 @@
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
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|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
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/**
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* @file STM32/GPIOv2/pal_lld.h
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* @brief STM32L1xx/STM32F2xx/STM32F4xx GPIO low level driver header.
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*
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* @addtogroup PAL
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* @{
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*/
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#ifndef _PAL_LLD_H_
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#define _PAL_LLD_H_
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Unsupported modes and specific modes */
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/*===========================================================================*/
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#undef PAL_MODE_RESET
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#undef PAL_MODE_UNCONNECTED
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#undef PAL_MODE_INPUT
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#undef PAL_MODE_INPUT_PULLUP
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#undef PAL_MODE_INPUT_PULLDOWN
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#undef PAL_MODE_INPUT_ANALOG
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#undef PAL_MODE_OUTPUT_PUSHPULL
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#undef PAL_MODE_OUTPUT_OPENDRAIN
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/**
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* @name STM32-specific I/O mode flags
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* @{
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*/
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#define PAL_STM32_MODE_MASK (3 << 0)
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#define PAL_STM32_MODE_INPUT (0 << 0)
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#define PAL_STM32_MODE_OUTPUT (1 << 0)
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#define PAL_STM32_MODE_ALTERNATE (2 << 0)
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#define PAL_STM32_MODE_ANALOG (3 << 0)
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#define PAL_STM32_OTYPE_MASK (1 << 2)
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#define PAL_STM32_OTYPE_PUSHPULL (0 << 2)
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#define PAL_STM32_OTYPE_OPENDRAIN (1 << 2)
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#define PAL_STM32_OSPEED_MASK (3 << 3)
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#define PAL_STM32_OSPEED_LOWEST (0 << 3)
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#if defined(STM32F0XX) || defined(STM32F30X) || defined(STM32F37X)
|
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#define PAL_STM32_OSPEED_MID (1 << 3)
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#else
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#define PAL_STM32_OSPEED_MID1 (1 << 3)
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#define PAL_STM32_OSPEED_MID2 (2 << 3)
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#endif
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#define PAL_STM32_OSPEED_HIGHEST (3 << 3)
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#define PAL_STM32_PUDR_MASK (3 << 5)
|
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#define PAL_STM32_PUDR_FLOATING (0 << 5)
|
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#define PAL_STM32_PUDR_PULLUP (1 << 5)
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#define PAL_STM32_PUDR_PULLDOWN (2 << 5)
|
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|
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#define PAL_STM32_ALTERNATE_MASK (15 << 7)
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#define PAL_STM32_ALTERNATE(n) ((n) << 7)
|
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|
||||
/**
|
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* @brief Alternate function.
|
||||
*
|
||||
* @param[in] n alternate function selector
|
||||
*/
|
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#define PAL_MODE_ALTERNATE(n) (PAL_STM32_MODE_ALTERNATE | \
|
||||
PAL_STM32_ALTERNATE(n))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Standard I/O mode flags
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief This mode is implemented as input.
|
||||
*/
|
||||
#define PAL_MODE_RESET PAL_STM32_MODE_INPUT
|
||||
|
||||
/**
|
||||
* @brief This mode is implemented as input with pull-up.
|
||||
*/
|
||||
#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP
|
||||
|
||||
/**
|
||||
* @brief Regular input high-Z pad.
|
||||
*/
|
||||
#define PAL_MODE_INPUT PAL_STM32_MODE_INPUT
|
||||
|
||||
/**
|
||||
* @brief Input pad with weak pull up resistor.
|
||||
*/
|
||||
#define PAL_MODE_INPUT_PULLUP (PAL_STM32_MODE_INPUT | \
|
||||
PAL_STM32_PUDR_PULLUP)
|
||||
|
||||
/**
|
||||
* @brief Input pad with weak pull down resistor.
|
||||
*/
|
||||
#define PAL_MODE_INPUT_PULLDOWN (PAL_STM32_MODE_INPUT | \
|
||||
PAL_STM32_PUDR_PULLDOWN)
|
||||
|
||||
/**
|
||||
* @brief Analog input mode.
|
||||
*/
|
||||
#define PAL_MODE_INPUT_ANALOG PAL_STM32_MODE_ANALOG
|
||||
|
||||
/**
|
||||
* @brief Push-pull output pad.
|
||||
*/
|
||||
#define PAL_MODE_OUTPUT_PUSHPULL (PAL_STM32_MODE_OUTPUT | \
|
||||
PAL_STM32_OTYPE_PUSHPULL)
|
||||
|
||||
/**
|
||||
* @brief Open-drain output pad.
|
||||
*/
|
||||
#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_STM32_MODE_OUTPUT | \
|
||||
PAL_STM32_OTYPE_OPENDRAIN)
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I/O Ports Types and constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief STM32 GPIO registers block.
|
||||
*/
|
||||
typedef struct {
|
||||
|
||||
volatile uint32_t MODER;
|
||||
volatile uint32_t OTYPER;
|
||||
volatile uint32_t OSPEEDR;
|
||||
volatile uint32_t PUPDR;
|
||||
volatile uint32_t IDR;
|
||||
volatile uint32_t ODR;
|
||||
volatile union {
|
||||
uint32_t W;
|
||||
struct {
|
||||
uint16_t set;
|
||||
uint16_t clear;
|
||||
} H;
|
||||
} BSRR;
|
||||
volatile uint32_t LCKR;
|
||||
volatile uint32_t AFRL;
|
||||
volatile uint32_t AFRH;
|
||||
} GPIO_TypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO port setup info.
|
||||
*/
|
||||
typedef struct {
|
||||
/** Initial value for MODER register.*/
|
||||
uint32_t moder;
|
||||
/** Initial value for OTYPER register.*/
|
||||
uint32_t otyper;
|
||||
/** Initial value for OSPEEDR register.*/
|
||||
uint32_t ospeedr;
|
||||
/** Initial value for PUPDR register.*/
|
||||
uint32_t pupdr;
|
||||
/** Initial value for ODR register.*/
|
||||
uint32_t odr;
|
||||
/** Initial value for AFRL register.*/
|
||||
uint32_t afrl;
|
||||
/** Initial value for AFRH register.*/
|
||||
uint32_t afrh;
|
||||
} stm32_gpio_setup_t;
|
||||
|
||||
/**
|
||||
* @brief STM32 GPIO static initializer.
|
||||
* @details An instance of this structure must be passed to @p palInit() at
|
||||
* system startup time in order to initialize the digital I/O
|
||||
* subsystem. This represents only the initial setup, specific pads
|
||||
* or whole ports can be reprogrammed at later time.
|
||||
*/
|
||||
typedef struct {
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
/** @brief Port A setup data.*/
|
||||
stm32_gpio_setup_t PAData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
/** @brief Port B setup data.*/
|
||||
stm32_gpio_setup_t PBData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
/** @brief Port C setup data.*/
|
||||
stm32_gpio_setup_t PCData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
/** @brief Port D setup data.*/
|
||||
stm32_gpio_setup_t PDData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
/** @brief Port E setup data.*/
|
||||
stm32_gpio_setup_t PEData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
/** @brief Port F setup data.*/
|
||||
stm32_gpio_setup_t PFData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
/** @brief Port G setup data.*/
|
||||
stm32_gpio_setup_t PGData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
/** @brief Port H setup data.*/
|
||||
stm32_gpio_setup_t PHData;
|
||||
#endif
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
/** @brief Port I setup data.*/
|
||||
stm32_gpio_setup_t PIData;
|
||||
#endif
|
||||
} PALConfig;
|
||||
|
||||
/**
|
||||
* @brief Width, in bits, of an I/O port.
|
||||
*/
|
||||
#define PAL_IOPORTS_WIDTH 16
|
||||
|
||||
/**
|
||||
* @brief Whole port mask.
|
||||
* @details This macro specifies all the valid bits into a port.
|
||||
*/
|
||||
#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
|
||||
|
||||
/**
|
||||
* @brief Digital I/O port sized unsigned type.
|
||||
*/
|
||||
typedef uint32_t ioportmask_t;
|
||||
|
||||
/**
|
||||
* @brief Digital I/O modes.
|
||||
*/
|
||||
typedef uint32_t iomode_t;
|
||||
|
||||
/**
|
||||
* @brief Port Identifier.
|
||||
* @details This type can be a scalar or some kind of pointer, do not make
|
||||
* any assumption about it, use the provided macros when populating
|
||||
* variables of this type.
|
||||
*/
|
||||
typedef GPIO_TypeDef * ioportid_t;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* I/O Ports Identifiers. */
|
||||
/* The low level driver wraps the definitions already present in the STM32 */
|
||||
/* firmware library. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief GPIO port A identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
|
||||
#define IOPORT1 GPIOA
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port B identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
|
||||
#define IOPORT2 GPIOB
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port C identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
|
||||
#define IOPORT3 GPIOC
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port D identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
|
||||
#define IOPORT4 GPIOD
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port E identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
|
||||
#define IOPORT5 GPIOE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port F identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
|
||||
#define IOPORT6 GPIOF
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port G identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
|
||||
#define IOPORT7 GPIOG
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port H identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
|
||||
#define IOPORT8 GPIOH
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief GPIO port I identifier.
|
||||
*/
|
||||
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
|
||||
#define IOPORT9 GPIOI
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Implementation, some of the following macros could be implemented as */
|
||||
/* functions, if so please put them in pal_lld.c. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief GPIO ports subsystem initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_init(config) _pal_lld_init(config)
|
||||
|
||||
/**
|
||||
* @brief Reads an I/O port.
|
||||
* @details This function is implemented by reading the GPIO IDR register, the
|
||||
* implementation has no side effects.
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @return The port bits.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_readport(port) ((port)->IDR)
|
||||
|
||||
/**
|
||||
* @brief Reads the output latch.
|
||||
* @details This function is implemented by reading the GPIO ODR register, the
|
||||
* implementation has no side effects.
|
||||
* @note This function is not meant to be invoked directly by the application
|
||||
* code.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @return The latched logical states.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_readlatch(port) ((port)->ODR)
|
||||
|
||||
/**
|
||||
* @brief Writes on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO ODR register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be written on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
|
||||
|
||||
/**
|
||||
* @brief Sets a bits mask on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO BSRR register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be ORed on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits))
|
||||
|
||||
/**
|
||||
* @brief Clears a bits mask on a I/O port.
|
||||
* @details This function is implemented by writing the GPIO BSRR register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] bits bits to be cleared on the specified port
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits))
|
||||
|
||||
/**
|
||||
* @brief Writes a group of bits.
|
||||
* @details This function is implemented by writing the GPIO BSRR register, the
|
||||
* implementation has no side effects.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] mask group mask
|
||||
* @param[in] offset the group bit offset within the port
|
||||
* @param[in] bits bits to be written. Values exceeding the group
|
||||
* width are masked.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writegroup(port, mask, offset, bits) \
|
||||
((port)->BSRR.W = ((~(bits) & (mask)) << (16 + (offset))) | \
|
||||
(((bits) & (mask)) << (offset)))
|
||||
|
||||
/**
|
||||
* @brief Pads group mode setup.
|
||||
* @details This function programs a pads group belonging to the same port
|
||||
* with the specified mode.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] mask group mask
|
||||
* @param[in] offset group bit offset within the port
|
||||
* @param[in] mode group mode
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_setgroupmode(port, mask, offset, mode) \
|
||||
_pal_lld_setgroupmode(port, mask << offset, mode)
|
||||
|
||||
/**
|
||||
* @brief Writes a logical state on an output pad.
|
||||
*
|
||||
* @param[in] port port identifier
|
||||
* @param[in] pad pad number within the port
|
||||
* @param[in] bit logical value, the value must be @p PAL_LOW or
|
||||
* @p PAL_HIGH
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
|
||||
|
||||
extern const PALConfig pal_default_config;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void _pal_lld_init(const PALConfig *config);
|
||||
void _pal_lld_setgroupmode(ioportid_t port,
|
||||
ioportmask_t mask,
|
||||
iomode_t mode);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_PAL */
|
||||
|
||||
#endif /* _PAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
Reference in New Issue
Block a user