mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-09-13 10:09:30 +00:00
fix ADSB RX weak signal on pro (#3282)
This commit is contained in:
qwer123
GitHub
@@ -125,10 +125,11 @@
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// ============================================================================
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// Canonical Default Values - SINGLE SOURCE OF TRUTH
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// ============================================================================
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/* Define the canonical RX defaults in ONE place */
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#define FPGA_RX_DEFAULT_DC_WIDTH 0x04 /* Typical for 40MHz stability */
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#define FPGA_RX_DEFAULT_ADAPT_RATE 0x08 /* Typical for 40MHz stability */
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#define FPGA_RX_DEFAULT_DIGITAL_GAIN 0x00 /* No shift initially */
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/* Define the canonical RX defaults in ONE place.
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* Matches fpga_init() in hackrf/firmware/common/fpga.c: the gateware only has
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* rx_decim and rx_pstep on the RX side, both starting at zero. */
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#define FPGA_RX_DEFAULT_DECIM 0x00 /* No decimation initially */
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#define FPGA_RX_DEFAULT_PSTEP 0x00 /* No quarter-rate shift initially */
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/* Define TX defaults */
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#define FPGA_TX_DEFAULT_NCO_CTRL 0x00 /* NCO disabled */
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@@ -221,12 +222,13 @@ static bool fpga_cdone_read(void) {
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// These functions allow reading/writing FPGA internal registers via SPI.
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// The FPGA bitstream implements a simple SPI register interface.
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//
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// FPGA Register Map:
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// Reg 1 (CTRL): DC_BLOCK(b0), QUARTER_SHIFT_EN(b1), QUARTER_SHIFT_UP(b2), PRBS(b6), TRIGGER_EN(b7)
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// Reg 2 (RX_DECIM): Decimation ratio [2:0]
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// Reg 3 (RX/TX): RX Digital Shift OR TX NCO Control
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// Reg 4 (RX_DC_BLOCK_WIDTH/TX_INTERP) [2:0]
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// Reg 5 (RX_DC_ADAPT_RATE/TX_PSTEP) [7:0]
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// FPGA Register Map (hackrf/firmware/fpga/top/standard.py):
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// Reg 1 (CTRL): DC_BLOCK(b0), PRBS(b6), TRIGGER_EN(b7)
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// Reg 2 (RX_DECIM): Decimation ratio, log2 [2:0]
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// Reg 3 (RX_PSTEP): QUARTER_SHIFT_EN(b6), QUARTER_SHIFT_UP(b7)
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// Reg 4 (TX_CTRL): NCO enable (b0)
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// Reg 5 (TX_INTRP): Interpolation ratio [2:0]
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// Reg 6 (TX_PSTEP): NCO phase step [7:0]
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//
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// SPI Protocol:
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// Read: Send [reg & 0x7F, 0x00, 0x00] -> value in byte 3
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@@ -369,22 +371,16 @@ void fpga_rx_enable_dc_block(bool enable) {
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}
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/* RX Functions with mode assertion */
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void fpga_rx_set_digital_gain(uint8_t shift) {
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/* Quarter-rate shift, register 0x03 bits [7:6]. Equivalent to
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* fpga_set_rx_quarter_shift_mode() in hackrf/firmware/common/fpga.c.
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* mode: 0b00 none, 0b11 up, 0b01 down. */
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void fpga_rx_set_quarter_shift_mode(uint8_t mode) {
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if (current_mode != FPGA_MODE_RX) {
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/* Log error or assert - wrong mode! */
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return;
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}
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fpga_register_write(FPGA_REG_SHARED_3, shift & FPGA_RX_GAIN_SHIFT_MASK);
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}
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void fpga_rx_set_dc_block_width(uint8_t width) {
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if (current_mode != FPGA_MODE_RX) return;
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fpga_register_write(FPGA_REG_SHARED_4, width & FPGA_RX_DC_WIDTH_MASK);
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}
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void fpga_rx_set_dc_adapt_rate(uint8_t rate) {
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if (current_mode != FPGA_MODE_RX) return;
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fpga_register_write(FPGA_REG_SHARED_5, rate);
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fpga_register_write(FPGA_REG_RX_PSTEP, (uint8_t)((mode & 0x03) << FPGA_RX_QUARTER_SHIFT_SHIFT));
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}
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// ============================================================================
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@@ -394,12 +390,12 @@ void fpga_rx_set_dc_adapt_rate(uint8_t rate) {
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/* TX Functions with mode assertion */
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void fpga_tx_set_nco_enable(bool enable) {
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if (current_mode != FPGA_MODE_TX) return;
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uint8_t val = fpga_register_read(FPGA_REG3_TX_NCO_CTRL);
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uint8_t val = fpga_register_read(FPGA_REG_TX_CONTROL);
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if (enable)
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val |= FPGA_TX_NCO_EN;
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else
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val &= ~FPGA_TX_NCO_EN;
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fpga_register_write(FPGA_REG3_TX_NCO_CTRL, val);
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fpga_register_write(FPGA_REG_TX_CONTROL, val);
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}
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void fpga_tx_set_interpolation(uint8_t ratio) {
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@@ -424,17 +420,17 @@ static void fpga_register_init(void) {
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current_mode = FPGA_MODE_RX;
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fpga_spi_write(FPGA_REG_CTRL, FPGA_CTRL_DC_BLOCK_EN);
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fpga_spi_write(FPGA_REG_DECIM, 0x00);
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fpga_spi_write(FPGA_REG_SHARED_3, FPGA_RX_DEFAULT_DIGITAL_GAIN);
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fpga_spi_write(FPGA_REG_SHARED_4, FPGA_RX_DEFAULT_DC_WIDTH);
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fpga_spi_write(FPGA_REG_SHARED_5, FPGA_RX_DEFAULT_ADAPT_RATE);
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fpga_spi_write(FPGA_REG_DECIM, FPGA_RX_DEFAULT_DECIM);
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fpga_spi_write(FPGA_REG_RX_PSTEP, FPGA_RX_DEFAULT_PSTEP);
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fpga_spi_write(FPGA_REG_TX_CONTROL, FPGA_TX_DEFAULT_NCO_CTRL);
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fpga_spi_write(FPGA_REG_TX_INTERP, FPGA_TX_DEFAULT_INTERP);
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/* Update cache */
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fpga_reg_cache[1] = FPGA_CTRL_DC_BLOCK_EN;
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fpga_reg_cache[2] = 0x00;
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fpga_reg_cache[3] = FPGA_RX_DEFAULT_DIGITAL_GAIN;
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fpga_reg_cache[4] = FPGA_RX_DEFAULT_DC_WIDTH;
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fpga_reg_cache[5] = FPGA_RX_DEFAULT_ADAPT_RATE;
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fpga_reg_cache[2] = FPGA_RX_DEFAULT_DECIM;
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fpga_reg_cache[3] = FPGA_RX_DEFAULT_PSTEP;
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fpga_reg_cache[4] = FPGA_TX_DEFAULT_NCO_CTRL;
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fpga_reg_cache[5] = FPGA_TX_DEFAULT_INTERP;
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}
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// ============================================================================
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@@ -16,10 +16,23 @@ extern "C" {
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#ifdef PRALINE
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/* RX path (legacy PRALINE software map kept for compatibility) */
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#define FPGA_REG_RX_DIGITAL_GAIN 0x03 /* Digital Shift / scaling (RX Mode) */
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#define FPGA_REG_RX_DC_BLOCK_WIDTH 0x04 /* Notch filter cutoff (RX Mode) */
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#define FPGA_REG_RX_DC_ADAPT_RATE 0x05 /* Settle time/Integration (RX Mode) */
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/*
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* RX path.
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*
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* NOTE: the register map below is the one the loaded bitstream actually
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* implements. Ground truth is hackrf/firmware/fpga/top/standard.py plus
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* hackrf/firmware/common/fpga_regs.def; Mayhem, hackrf_usb and debug_for_adsb
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* all load a byte-identical praline_fpga.bin, so that map applies here too.
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*
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* An earlier "legacy PRALINE software map" claimed register 0x03 was an RX
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* digital gain and 0x04/0x05 were DC-block width / adaptation rate. The
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* gateware has none of those: 0x03 is rx_pstep (whose top two bits are the
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* quarter-rate shift) and 0x04/0x05 are TX registers. Writing the old "RX DC
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* width" value of 0x01 to 0x04 actually set tx_ctrl[0] and switched the TX NCO
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* on, and every write of the fictional digital gain to 0x03 cleared the
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* quarter shift.
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*/
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#define FPGA_REG_RX_PSTEP 0x03 /* RX phase step; bits [7:6] = quarter shift */
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/*
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* TX path must match the currently built PRALINE standard gateware in
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@@ -43,70 +56,55 @@ typedef enum {
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/*
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* FPGA Register Addresses
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* NOTE:
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* The currently loaded PRALINE standard gateware uses:
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* 0x01 CTRL
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* 0x02 RX_DECIM
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* 0x03 RX_DIGITAL_GAIN (RX) / TX_NCO_CTRL (TX)
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* 0x04 TX_CTRL
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* 0x05 TX_INTRP
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* 0x06 TX_PSTEP
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*
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* From hackrf/firmware/fpga/top/standard.py (spi_regs.add_register):
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* 0x01 ctrl 8 bits
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* 0x02 rx_decim 3 bits
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* 0x03 rx_pstep 8 bits
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* 0x04 tx_ctrl 1 bit
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* 0x05 tx_intrp 3 bits
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* 0x06 tx_pstep 8 bits
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*
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* There is no RX gain register: rx_decim selects half-band FIR stages
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* (hbfir1..hbfir5), which are unity-gain, so there is no CIC bit growth to
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* renormalise.
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*/
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#define FPGA_REG_CTRL 0x01 /* Control register */
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#define FPGA_REG_DECIM 0x02 /* RX decimation */
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#define FPGA_REG_SHARED_3 0x03 /* Legacy shared register */
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#define FPGA_REG_SHARED_4 0x04 /* Legacy shared register */
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#define FPGA_REG_SHARED_5 0x05 /* Legacy shared register */
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#define FPGA_REG_SHARED_6 0x06 /* TX phase step */
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#define FPGA_REG_CTRL 0x01 /* Control register */
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#define FPGA_REG_DECIM 0x02 /* RX decimation (log2, bits [2:0]) */
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/* 0x03..0x06 are FPGA_REG_RX_PSTEP / FPGA_REG_TX_CONTROL /
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* FPGA_REG_TX_INTERP / FPGA_REG_TX_PHASE_STEP, defined above. */
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/*
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* Register 1 (CTRL) Bit Definitions
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* standard.py: ctrl[0] -> dc_block.enable, ctrl[6] -> prbs, ctrl[7] -> trigger_en.
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* Nothing else in this register is decoded.
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*/
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#define FPGA_CTRL_DC_BLOCK_EN (1 << 0) /* DC block enable */
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#define FPGA_CTRL_QUARTER_SHIFT_EN (1 << 1) /* Quarter-rate shift enable */
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#define FPGA_CTRL_QUARTER_SHIFT_UP (1 << 2) /* Shift direction: 1=up, 0=down */
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#define FPGA_CTRL_TX_MODE (1 << 5) /* TX mode indicator (if applicable) */
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#define FPGA_CTRL_PRBS_EN (1 << 6) /* PRBS test mode */
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#define FPGA_CTRL_TRIGGER_EN (1 << 7) /* External trigger enable */
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#define FPGA_CTRL_DC_BLOCK_EN (1 << 0) /* DC block enable */
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#define FPGA_CTRL_PRBS_EN (1 << 6) /* PRBS test mode */
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#define FPGA_CTRL_TRIGGER_EN (1 << 7) /* External trigger enable */
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/*
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* Register 3 Dual-Purpose Definitions
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* Register 3 (RX_PSTEP) Bit Definitions
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* standard.py: rx_pstep[6] -> quarter_shift.enable, rx_pstep[7] -> quarter_shift.up.
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* Same encoding as fpga_quarter_shift_mode_t << 6 in hackrf/firmware/common/fpga.c.
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*/
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/* RX Mode: Digital gain/shift */
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#define FPGA_REG3_RX_DIGITAL_GAIN 0x03
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#define FPGA_RX_GAIN_SHIFT_MASK 0x0F /* Bits [3:0] - shift amount */
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/* Position of that 2-bit field inside rx_pstep, for direct register writes. */
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#define FPGA_RX_QUARTER_SHIFT_SHIFT 6
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#define FPGA_RX_QUARTER_SHIFT_MASK 0xC0
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/* TX Mode: NCO control */
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#define FPGA_REG3_TX_NCO_CTRL 0x03
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#define FPGA_TX_NCO_EN (1 << 0) /* NCO enable */
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#define FPGA_TX_NCO_INVERT (1 << 1) /* Invert spectrum */
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/* Mode values, matching fpga_quarter_shift_mode_t in
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* hackrf/firmware/common/fpga.h. Pass these to
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* fpga_rx_set_quarter_shift_mode(), which shifts them into place. */
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#define FPGA_QUARTER_SHIFT_MODE_NONE 0b00
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#define FPGA_QUARTER_SHIFT_MODE_UP 0b11
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#define FPGA_QUARTER_SHIFT_MODE_DOWN 0b01
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/*
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* Register 4 Dual-Purpose Definitions
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* Register 4 (TX_CTRL) / 5 (TX_INTRP) / 6 (TX_PSTEP) Bit Definitions
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*/
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/* RX Mode: DC block notch width */
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#define FPGA_REG4_RX_DC_WIDTH 0x04
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#define FPGA_RX_DC_WIDTH_MASK 0x07 /* Bits [2:0] */
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/* TX Mode: Interpolation ratio */
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#define FPGA_REG4_TX_INTERP 0x05
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#define FPGA_TX_INTERP_MASK 0x07 /* Bits [2:0] */
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/*
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* Register 5 Dual-Purpose Definitions
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*/
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/* RX Mode: DC block adaptation rate */
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#define FPGA_REG5_RX_DC_RATE 0x05
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#define FPGA_RX_DC_RATE_MASK 0xFF /* Bits [7:0] */
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/* TX Mode: NCO phase step (frequency) */
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#define FPGA_REG5_TX_PHASE_STEP 0x06
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#define FPGA_TX_PHASE_STEP_MASK 0xFF /* Bits [7:0] */
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/* Export default values so other methods can use them */
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#define FPGA_RX_DEFAULT_DIGITAL_GAIN 0x00
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#define FPGA_RX_DEFAULT_DC_WIDTH 0x04
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#define FPGA_RX_DEFAULT_ADAPT_RATE 0x08
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#define FPGA_TX_NCO_EN (1 << 0) /* tx_ctrl[0]: NCO enable */
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#define FPGA_TX_INTERP_MASK 0x07 /* tx_intrp bits [2:0] */
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#define FPGA_TX_PHASE_STEP_MASK 0xFF /* tx_pstep bits [7:0] */
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/*
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* Core Functions
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@@ -133,9 +131,8 @@ void fpga_register_write(uint8_t reg, uint8_t value);
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* RX Mode Functions (only valid when mode == FPGA_MODE_RX)
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*/
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void fpga_rx_set_decimation(uint8_t ratio);
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void fpga_rx_set_digital_gain(uint8_t shift);
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void fpga_rx_set_dc_block_width(uint8_t width);
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void fpga_rx_set_dc_adapt_rate(uint8_t rate);
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/* mode is the gateware encoding: 0b00 none, 0b11 up, 0b01 down. */
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void fpga_rx_set_quarter_shift_mode(uint8_t mode);
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void fpga_rx_enable_dc_block(bool enable);
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/*
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@@ -154,12 +151,13 @@ void fpga_tx_set_phase_step(uint8_t step);
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* reg: Register number (1-5)
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* Returns: Register value, or 0xFF if invalid register
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*
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* FPGA Register Map:
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* Reg 1 (CTRL): DC_BLOCK(b0), QUARTER_SHIFT_EN(b1), QUARTER_SHIFT_UP(b2), PRBS(b6), TRIGGER_EN(b7)
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* Reg 2 (RX_DECIM): Decimation ratio [2:0]
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* Reg 3 (RX/TX): RX Digital Shift OR TX NCO Control
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* Reg 4 (RX_DC_BLOCK_WIDTH/TX_INTERP) [2:0]
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* Reg 5 (RX_DC_ADAPT_RATE/TX_PSTEP) [7:0]
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* FPGA Register Map (hackrf/firmware/fpga/top/standard.py):
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* Reg 1 (CTRL): DC_BLOCK(b0), PRBS(b6), TRIGGER_EN(b7)
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* Reg 2 (RX_DECIM): Decimation ratio, log2 [2:0]
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* Reg 3 (RX_PSTEP): QUARTER_SHIFT_EN(b6), QUARTER_SHIFT_UP(b7)
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* Reg 4 (TX_CTRL): NCO_EN(b0)
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* Reg 5 (TX_INTRP): Interpolation ratio, log2 [2:0]
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* Reg 6 (TX_PSTEP): NCO phase step [7:0]
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*/
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uint8_t fpga_debug_register_read(uint8_t reg);
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