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Legacy Initialization, Analog Audio App, and Aliasing fixes. (#3052)

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* Added PRO button to analog_audio.cpp for debugging metallic ringing sounds in Audio app. Ensured consitency to 4MHz in analog_audio.cpp

* Restored blutooth after loss.

* Added several sampling rates to analog_audio for testing.

* Ran format-code.sh

* Fixed 0x03 mode for DC/Q-INV/Q-SHFT being set at every tuning and sample rate change. This was the root cause for loss of bluetooth before. Sample rate, and frequency can now be changed without need for manually resetting DC/Q-INV/Q-SHIFT settings. Updated method for setting frequncies in praline so that we have more testing options.

* Ran format-code.sh and cleaned up stale comments.

* Addressed comments, and removed commented line, opting for higher register values, 5E and 5D. Added WFM Debug View to support testing demodulation ringing.

* Addressed comments in PR conversation to clean comments and ensure consistency at initializtion accross updated methods and displays.

* Ran format-code.sh

* Set initial legacy state. Improved readability of clocking initialization settings. Updated set_sampling_frequency, and udpate_bandwidth to set decimation values in the fpga_registers to avoid aliasing in low band frequencies.

* Updated clock_manager to use correct clock and clock parameters for audio pll. Ran format-code.sh.
This commit is contained in:
stafur
2026-02-27 23:43:19 -05:00
committed by GitHub
parent 56adca3bf6
commit b2bf0f2459
10 changed files with 179 additions and 143 deletions
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firmware/application/radio.cpp
+2 -2
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@@ -172,7 +172,7 @@ void init() {
/* Initialize FPGA registers - DC_BLOCK must be enabled for RX */
// debug::fpga::init();
// These FPGA registers control DC_BLOCK, Q-Inv, QUARTER SHIFT, and Decimation.
fpga_debug_register_write(1, 0x01); // DC_BLOCK=1, QUARTER_SHIFT=0, Q_INVERT=0
fpga_debug_register_write(1, 0x00); // DC_BLOCK=1, QUARTER_SHIFT=0, Q_INVERT=0
fpga_debug_register_write(2, 0x00); // RX_DECIM=No Decim
fpga_debug_register_write(3, 0x00); // TX_CTRL=0
fpga_debug_register_write(4, 0x00); // TX_INTRP=0
@@ -512,7 +512,7 @@ void register_write(const size_t register_number, uint32_t value) {
void init() {
// Initialize FPGA registers after bitstream load
// DC_BLOCK (bit 0) must be enabled for RX to work
fpga_debug_register_write(1, 0x01); // CTRL: DC_BLOCK=1
fpga_debug_register_write(1, 0x00); // CTRL: DC_BLOCK=1
fpga_debug_register_write(2, 0x00); // RX_DECIM: no decimation
fpga_debug_register_write(3, 0x00); // TX_CTRL: NCO disabled
fpga_debug_register_write(4, 0x00); // TX_INTRP: no interpolation