mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-08-16 04:43:28 +00:00
Legacy Initialization, Analog Audio App, and Aliasing fixes. (#3052)
* Added PRO button to analog_audio.cpp for debugging metallic ringing sounds in Audio app. Ensured consitency to 4MHz in analog_audio.cpp * Restored blutooth after loss. * Added several sampling rates to analog_audio for testing. * Ran format-code.sh * Fixed 0x03 mode for DC/Q-INV/Q-SHFT being set at every tuning and sample rate change. This was the root cause for loss of bluetooth before. Sample rate, and frequency can now be changed without need for manually resetting DC/Q-INV/Q-SHIFT settings. Updated method for setting frequncies in praline so that we have more testing options. * Ran format-code.sh and cleaned up stale comments. * Addressed comments, and removed commented line, opting for higher register values, 5E and 5D. Added WFM Debug View to support testing demodulation ringing. * Addressed comments in PR conversation to clean comments and ensure consistency at initializtion accross updated methods and displays. * Ran format-code.sh * Set initial legacy state. Improved readability of clocking initialization settings. Updated set_sampling_frequency, and udpate_bandwidth to set decimation values in the fpga_registers to avoid aliasing in low band frequencies. * Updated clock_manager to use correct clock and clock parameters for audio pll. Ran format-code.sh.
This commit is contained in:
stafur
GitHub
@@ -109,6 +109,15 @@ constexpr si5351::MultisynthFractional si5351_ms_0_20m {
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};
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constexpr auto si5351_ms_0_20m_reg = si5351_ms_0_20m.reg(0);
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*/
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constexpr si5351::MultisynthFractional si5351_ms_0_4m{
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.f_src = si5351_vco_f, // 800,000,000 Hz
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.a = 100, // Integer divider 100
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.b = 0,
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.c = 1,
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.r_div = 1 // Final R-divider: 2^1 = 2
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};
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constexpr si5351::MultisynthFractional si5351_ms_0_8m{
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.f_src = si5351_vco_f,
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.a = 50,
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@@ -398,12 +407,35 @@ void ClockManager::init_clock_generator() {
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#endif
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#ifdef PRALINE
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/* PRALINE uses Si5351A with:
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* CLK0 = AFE_CLK (codec/FPGA sample clock)
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* CLK1 = SCT_CLK (FPGA timing clock at 2x sample rate)
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* CLK4 = second IF (MAX2831)
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* CLK5 = first IF (RFFC5072)
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* Uses PLLA on XTAL only (no CLKIN support).
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/* * Praline HackRF Pro Clock Assignments (800 MHz VCO Configuration)
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* VCO Frequency: 800,000,000 Hz (Master Reference)
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* * CLK0: AFE_CLK (MAX5864 Codec & FPGA ADC Interface)
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* - Initialized to: 4,000,000 Hz (si5351_ms_4m)
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* - Divider: 100 (Integer), R_DIV: 2 (r_div=1)
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* - Note: Defines hardware sample rate. Essential for WFM purity.
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* * CLK1: SCT_CLK (iCE40 FPGA System/Timing Clock)
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* - Initialized to: 10,000,000 Hz (si5351_ms_10m)
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* - Divider: 80 (Integer), R_DIV: 1 (r_div=0)
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* - Note: Timing for SGPIO data bus; scales to 2x SR in wideband modes.
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* * CLK2: MCU_CLKIN (LPC43xx MCU External Clock Input)
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* - Initialized to: 10,000,000 Hz (si5351_ms_10m)
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* - Divider: 80 (Integer), R_DIV: 1 (r_div=0)
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* - Note: Synchronizes MCU processing to the RF clock tree.
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* * CLK3: SG_CLK (Switching Regulator/Internal Logic Sync)
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* - Initialized to: 10,000,000 Hz (si5351_ms_10m)
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* - Divider: 80 (Integer), R_DIV: 1 (r_div=0)
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* - Note: Used for internal FPGA logic/gateware synchronization.
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* * CLK4: P_CLK (Peripheral/Expansion Clock)
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* - Configured via: si5351c_ms_4_reg
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* - Note: Routed to expansion headers for external hardware sync.
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* * CLK5: AUX_CLK (Auxiliary reference for secondary logic)
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* - Configured via: si5351c_ms_5_reg
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* - Note: Provides additional timing flexibility for the iCE40 FPGA.
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* * CLK6/7: Unused / Power-Down
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* - State: Disabled (si5351a_ms6_7_off_reg)
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* - Note: Kept OFF to reduce EMI/RFI near the RF front-end.
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* * CLKOUT: Optional external clock output on the header.
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*/
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/* Step 1: Write PLL A configuration (800 MHz VCO from 25 MHz XTAL) */
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@@ -417,25 +449,13 @@ void ClockManager::init_clock_generator() {
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}
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/* Step 2: Write multisynth configurations using single-byte writes */
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clock_generator.write_ms_single_byte(0, si5351_ms_0_8m); // MS0 = divider 50, r_div=1 for 8 MHz
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clock_generator.write_ms_single_byte(1, si5351_ms_16m); // MS1 = divider 50, r_div=0 for 16 MHz
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/* CLK4 and CLK5 - use single-byte writes too */
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{
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const auto& ms4_regs = si5351c_ms_4_reg;
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const uint8_t base_reg = ms4_regs[0];
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for (size_t i = 1; i < ms4_regs.size(); i++) {
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clock_generator.write_register(base_reg + i - 1, ms4_regs[i]);
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}
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}
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{
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const auto& ms5_regs = si5351c_ms_5_reg;
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const uint8_t base_reg = ms5_regs[0];
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for (size_t i = 1; i < ms5_regs.size(); i++) {
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clock_generator.write_register(base_reg + i - 1, ms5_regs[i]);
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}
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}
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clock_generator.write(si5351a_ms6_7_off_reg); // MS6/7 off - short write is OK
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// These cover all active channels on the Praline board
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clock_generator.write_ms_single_byte(0, si5351_ms_0_4m); // CLK0: Codec (4 MHz)
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clock_generator.write_ms_single_byte(1, si5351_ms_10m); // CLK1: FPGA Timing (10 MHz)
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clock_generator.write_ms_single_byte(2, si5351_ms_10m); // CLK2: MCU Input (10 MHz)
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clock_generator.write_ms_single_byte(3, si5351_ms_10m); // CLK3: Logic Sync (10 MHz)
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clock_generator.write_ms_single_byte(4, si5351_ms_40m); // CLK4: First IF (40 MHz)
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clock_generator.write_ms_single_byte(5, si5351_ms_40m); // CLK5: Second IF (40 MHz)
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/* Step 3: NOW set clock control registers (AFTER multisynths per HackRF reference) */
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const auto ref_pll = ClockControl::MultiSynthSource::PLLA;
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@@ -489,21 +509,6 @@ void ClockManager::init_clock_generator() {
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// CRITICAL: Add delay to ensure Si5351 writes complete before I2C bus stops
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chThdSleepMilliseconds(100);
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// ===== ADD THIS SAFETY BLOCK =====
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// Pre-configure CLK4/CLK5 with correct settings including inversion.
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// This ensures the registers have correct values even if enable_if_clocks()
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// is not called or fails. The clocks will still be powered off until
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// enable_if_clocks() enables the outputs.
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// CLK5: OFF (for now), Integer, PLLA, INVERTED, MS_Self, 6mA = 0xDE
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// (Same as 0x5E but with bit 7 set for power off)
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clock_generator.write_register(21, 0xDE);
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// CLK4: OFF (for now), Integer, PLLA, INVERTED, MS_Self, 4mA = 0xDD
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clock_generator.write_register(20, 0xDD);
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// ===== END SAFETY BLOCK =====
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#else
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// Wait for PLL(s) to lock - with timeout to prevent hang
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uint8_t device_status_mask = hackrf_r9
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@@ -642,27 +647,6 @@ void ClockManager::disable_codec_clocks() {
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void ClockManager::enable_if_clocks() {
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#ifdef PRALINE
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/* PRALINE: CLK4=MAX2831, CLK5=RFFC5072
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*
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* Force-write complete configuration to guarantee correct setup.
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* Added force-write to verify correct registers are applying necessary register clock settings.
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*/
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// Configure and enable CLK4 (MAX2831)
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// Register 20: ON, Integer, PLLA, INVERTED, MS_Self, 4mA = 0x5D
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clock_generator.write_register(20, 0x5D);
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// Configure and enable CLK5 (RFFC5072) - CRITICAL!
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// Register 21: ON, Integer, PLLA, INVERTED, MS_Self, 6mA = 0x5E
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clock_generator.write_register(21, 0x5E);
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// Enable outputs (register 3, bits 4 and 5 = 0)
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uint8_t reg3 = clock_generator.read_register(3);
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reg3 &= ~0x30;
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clock_generator.write_register(3, reg3);
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chThdSleepMilliseconds(10);
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/* PRALINE uses CLK5 (first IF) and CLK4 (second IF) */
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clock_generator.enable_clock(clock_generator_output_og_first_if);
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clock_generator.enable_output_mask(1U << clock_generator_output_og_first_if);
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@@ -710,15 +694,45 @@ void ClockManager::set_sampling_frequency(const uint32_t frequency) {
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/* PRALINE: Match HackRF USB sample_rate_frac_set()
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* Reference: hackrf_usb radio.c lines 29-91, hackrf_core.c lines 501-685 */
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_base_band_frequency = frequency;
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_base_band_frequency = frequency; // Store frequency for StatusViews
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// Set FPGA decimation to 0 (no decimation) for direct passthrough
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fpga_debug_register_write(2, 0x00);
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/*
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* PRALINE sample rate strategy from GSG hackrf_usb radio.c:
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*
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* 1. Run ADC at the highest rate possible (up to 40 MHz)
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* 2. Use FPGA decimation to achieve desired output rate
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* 3. This makes the analog LPF effective at rejecting aliases
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* 4. Re-apply frequency after to reconfigure LPF bandwidth
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*/
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// 20 MHz, since GSG reference of 40MHz caused shifts at certain values.
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constexpr uint32_t MAX_AFE_RATE = 20000000;
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constexpr uint8_t MAX_N = 5; // Max decimation = 2^5 = 32
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// Calculate optimal decimation factor for RX
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// Start with n=1 (minimum decimation of 2) per reference
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uint8_t n = 1;
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uint32_t afe_rate_x2 = 2 * frequency;
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while ((afe_rate_x2 <= MAX_AFE_RATE) && (n < MAX_N)) {
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afe_rate_x2 <<= 1;
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n++;
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}
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// Store decimation factor for potential use elsewhere
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_resampling_n = n;
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// The actual AFE rate = frequency * 2^n
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uint32_t afe_rate = frequency << n;
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// Set FPGA RX decimation register
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fpga_debug_register_write(2, n);
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radio::invalidate_spi_config();
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// The following was originally from @kitty. Adopting for testing radio.
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clock_generator.set_ms_frequency(0, frequency * 2, si5351_vco_f, 1); // CLK0: r_div=1 (÷2)
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clock_generator.set_ms_frequency(1, frequency * 2, si5351_vco_f, 0); // CLK1: r_div=0 (÷1)
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// Configure Si5351 clocks
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clock_generator.set_ms_frequency(0, afe_rate * 2, si5351_vco_f, 1); // CLK0: AFE_CLK
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clock_generator.set_ms_frequency(1, afe_rate * 2, si5351_vco_f, 0); // CLK1: SCT_CLK
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#else
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/* Codec clock is at sampling frequency, CPLD and SGPIO clocks are at
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* twice the frequency, and derived from the MS0 synth. So it's only
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@@ -797,27 +811,37 @@ void ClockManager::start_audio_pll() {
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* 12MHz * 1024 / 25 = 491.52MHz
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* MSEL=1024, NSEL=25, PSEL=20
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*/
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cgu::pll0audio::ctrl({
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.pd = 1,
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.bypass = 0,
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.directi = 0,
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.directo = 0,
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.clken = 0,
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.frm = 0,
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.autoblock = 1,
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.pllfract_req = 0,
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.sel_ext = 1,
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.mod_pd = 1,
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.clk_sel = cgu::CLK_SEL::XTAL,
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});
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cgu::pll0audio::mdiv({
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.mdec = 22625UL, // MDEC for MSEL=1024
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.mdec = 22625UL, // Encoded value for MSEL=1024
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});
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cgu::pll0audio::np_div({
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.pdec = 31, // PSEL=20
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.ndec = 69, // NDEC for NSEL=25
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.pdec = 31, // Encoded value for PSEL=20
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.ndec = 69, // Encoded value for NSEL=25
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});
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cgu::pll0audio::frac({
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.pllfract_ctrl = 0,
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});
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cgu::pll0audio::power_up();
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// Praline Fix: Wait for lock with a safety timeout
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{
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uint32_t timeout = 100000;
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while (!cgu::pll0audio::is_locked() && timeout > 0) {
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timeout--;
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}
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}
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cgu::pll0audio::clock_enable();
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/* Route the 12.288MHz PLL to the Base Audio Clock */
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// PD = 0 enables the clock; AUTOBLOCK = 1 prevents glitches during clock switching
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LPC_CGU->BASE_AUDIO_CLK.PD = 0;
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LPC_CGU->BASE_AUDIO_CLK.AUTOBLOCK = 1;
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LPC_CGU->BASE_AUDIO_CLK.CLK_SEL = toUType(cgu::CLK_SEL::PLL0AUDIO);
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#else
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cgu::pll0audio::ctrl({
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.pd = 1,
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