Sampling frequency and Receiver Model tweaks. (#3053)

firmware/application/clock_manager.cpp

@@ -730,8 +730,8 @@ void ClockManager::set_sampling_frequency(const uint32_t frequency) {
     radio::invalidate_spi_config();
 
     // Configure Si5351 clocks
-    clock_generator.set_ms_frequency(0, afe_rate * 2, si5351_vco_f, 1);  // CLK0: AFE_CLK
+    clock_generator.set_ms_frequency(0, afe_rate * 4, si5351_vco_f, 2);  // CLK0: AFE_CLK
-    clock_generator.set_ms_frequency(1, afe_rate * 2, si5351_vco_f, 0);  // CLK1: SCT_CLK
+    clock_generator.set_ms_frequency(1, afe_rate * 4, si5351_vco_f, 1);  // CLK1: SCT_CLK
 
 #else
     /* Codec clock is at sampling frequency, CPLD and SGPIO clocks are at

firmware/application/radio.cpp

@@ -79,6 +79,15 @@ static constexpr SPIConfig ssp_config_max283x = {
         CR0_CLOCKRATE(ssp_scr(ssp1_pclk_f, ssp1_cpsr, max283x_spi_f) + 3) | CR0_FRFSPI | CR0_DSS9BIT,
     .cpsr = ssp1_cpsr,
 };
+
+static max283x::MAX283x* transceiver = nullptr;
+
+void set_rx_buff_vcm(const size_t v) {
+    if (transceiver) {
+        transceiver->set_rx_buff_vcm(v);
+    }
+}
+
 #else
 /* MAX2837/MAX2839 use 16-bit SPI transfers */
 static constexpr SPIConfig ssp_config_max283x = {

firmware/application/radio.hpp

@@ -64,6 +64,7 @@ void disable();
 
 #ifdef PRALINE
 void invalidate_spi_config();
+void set_rx_buff_vcm(const size_t v);
 #endif
 
 namespace debug {

firmware/application/receiver_model.cpp

@@ -242,6 +242,14 @@ void ReceiverModel::set_normalized_headphone_volume(uint8_t v) {
 void ReceiverModel::enable() {
     enabled_ = true;
     radio::set_direction(rf::Direction::Receive);
+
+#ifdef PRALINE
+    /* Anchor the Common Mode Voltage (VCM) to 1.2V.
+     * This stabilizes the electrical floor of the I/Q signals.
+     */
+    radio::set_rx_buff_vcm(1);
+#endif
+
     update_tuning_frequency();
     update_antenna_bias();
     update_rf_amp();