Change charge display off to sleep (#3153)

firmware/application/event_m0.cpp

@@ -37,8 +37,20 @@
 
 #include "ch.h"
 
-#include "lpc43xx_cpp.hpp"
+#include "hackrf_gpio.hpp"
-using namespace lpc43xx;
+using namespace hackrf::one;
+
+#include "irq_rtc.hpp"
+
+#include "i2c_lld.h"
+
+#include "i2cdevmanager.hpp"
+#include "i2cdev_ppmod.hpp"
+
+#include "lpc43xx.inc"
+#include "nvic.h"
+#include "lpc43xx_m0.h"
+#include "rffc507x_spi.hpp"
 
 #include <array>
 
@@ -134,8 +146,195 @@ void EventDispatcher::set_display_sleep(const bool sleep) {
         // Let frame sync handler turn on backlight after repaint.
     }
     EventDispatcher::display_sleep = sleep;
+}
+
+void EventDispatcher::charge_deep_sleep(const bool sleep) {
+    bool detect = false;
+    uint8_t valid_mask = 0;
+    uint8_t percent = 0;
+    uint16_t voltage = 0;
+    int32_t current = 0;
+
+    constexpr I2CConfig i2c_config_12mhz{
+        .high_count = 15,
+        .low_count = 15,
     };
 
+    if (sleep) {
+        auto dev = (i2cdev::I2cDev_PPmod*)i2cdev::I2CDevManager::get_dev_by_model(I2C_DEVMDL::I2CDECMDL_PPMOD);
+        if (dev) dev->send_poweroff_command();
+
+        rffc507x::spi::SPI().power_down();
+        portapack::shutdown(false, true);
+
+        // Unmount SD card and stop driver
+        f_mount(nullptr, reinterpret_cast<const TCHAR*>(_T("")), 0);
+        sdcDisconnect(&SDCD1);
+        sdcStop(&SDCD1);
+
+        // Signal application shutdown
+        ShutdownMessage shutdown_message;
+        shared_memory.application_queue.push(shutdown_message);
+        shared_memory.baseband_message = nullptr;
+
+        // Disable core interrupts and system tick
+        nvicDisableVector(DMA_IRQn);
+        nvicDisableVector(M4CORE_IRQn);
+        chSysDisable();
+        systick_stop();
+
+        SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk;
+
+#ifdef PRALINE
+        // Power management and GPIO configuration for Praline hardware
+        gpio_vaa_disable.set();
+        gpio_1v2_enable.clear();
+        LPC_GPIO->DIR[0] &= ~0xFFFF4000;
+        LPC_GPIO->DIR[1] &= ~0xFFFF1000;
+        LPC_GPIO->DIR[2] &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) | (1 << 6) | (1 << 0));
+        LPC_GPIO->DIR[3] &= ~((1 << 7) | (1 << 5));
+        LPC_GPIO->DIR[5] &= ~(1 << 16);
+#else
+        // Power management and GPIO configuration for legacy hardware
+        gpio_og_vaa_disable.set();
+        gpio_r9_vaa_disable.clear();
+        LPC_GPIO->DIR[0] &= ~0xFFFF4000;
+        LPC_GPIO->DIR[1] &= ~0xFFFF1000;
+        LPC_GPIO->DIR[2] &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) | (1 << 6) | (1 << 0));
+        LPC_GPIO->DIR[3] &= ~((1 << 7) | (1 << 5));
+        LPC_GPIO->DIR[5] &= ~(1 << 16);
+#endif
+
+        // Power down peripherals (CGU cleanup)
+        LPC_RGU->RESET_CTRL[0] = (1 << 5);  // USB0 Reset
+        LPC_CGU->PLL0USB_CTRL.PD = 1;
+        LPC_CGU->BASE_USB0_CLK.PD = 1;
+        LPC_CREG->CREG0 |= (1 << 5);
+
+        LPC_CGU->BASE_USB1_CLK.PD = 1;
+        LPC_CGU->BASE_UART0_CLK.PD = 1;
+        LPC_CGU->BASE_UART1_CLK.PD = 1;
+        LPC_CGU->BASE_UART2_CLK.PD = 1;
+        LPC_CGU->BASE_UART3_CLK.PD = 1;
+        LPC_CGU->BASE_SPI_CLK.PD = 1;
+        LPC_CGU->BASE_PERIPH_CLK.PD = 1;
+        LPC_CGU->BASE_SDIO_CLK.PD = 1;
+        LPC_CGU->BASE_SSP0_CLK.PD = 1;
+        LPC_CGU->BASE_SSP1_CLK.PD = 1;
+        LPC_CGU->BASE_LCD_CLK.PD = 1;
+        LPC_CGU->BASE_OUT_CLK.PD = 1;
+
+        (*(volatile uint32_t*)(&LPC_CGU->PLL0AUDIO_CTRL)) |= (1 << 0);
+
+        LPC_ADC0->CR &= ~(1 << 21);
+        LPC_ADC1->CR &= ~(1 << 21);
+        led_rx.off();
+        led_usb.off();
+
+        rtc_wakeup_init();
+        NVIC_EnableIRQ(I2C0_OR_I2C1_IRQn);
+
+        while (1) {
+            // --- Battery Status Check (I2C) ---
+            detect = battery::BatteryManagement::isDetected();
+            if (detect) {
+                battery::BatteryManagement::getBatteryInfo(valid_mask, percent, voltage, current);
+
+                bool is_full = (valid_mask == 31 && percent == 100 && current <= 10) ||
+                               (valid_mask == 1 && percent == 100);
+
+                if (is_full) {
+                    // Case 1: Battery full (All LEDs off)
+                    led_rx.off();
+                    led_tx.off();
+                } else if ((voltage < 4150 && current < 10) || valid_mask == 0) {
+                    // Case 2: Not full but low current draw (<10mA) -> Charging error
+                    led_tx.on();  // LED indicates error/idle
+                    led_rx.off();
+                } else {
+                    // Case 3: Actively charging
+                    led_rx.on();  // LED indicates charging
+                    led_tx.off();
+                }
+            } else {
+                // Case 4: Battery IC not detected -> Error or H2 or older, so don't show that as an error.
+                led_tx.on();
+                led_rx.on();
+            }
+
+            // Shut down I2C and power down the APB bus for sleep
+            portapack::i2c0.stop();
+            LPC_CGU->BASE_APB1_CLK.PD = 1;
+
+            // Save interrupt states before mass disable
+            uint32_t saved_iser0 = NVIC->ISER[0];
+            uint32_t saved_iser1 = NVIC->ISER[1];
+            uint32_t saved_iser2 = NVIC->ISER[2];
+
+            // Disable and clear all pending interrupts
+            NVIC->ICER[0] = 0xFFFFFFFF;
+            NVIC->ICER[1] = 0xFFFFFFFF;
+            NVIC->ICER[2] = 0xFFFFFFFF;
+
+            NVIC->ICPR[0] = 0xFFFFFFFF;
+            NVIC->ICPR[1] = 0xFFFFFFFF;
+            NVIC->ICPR[2] = 0xFFFFFFFF;
+
+            // Re-enable only necessary wakeup sources
+            NVIC_EnableIRQ(RTC_IRQn);
+            NVIC_EnableIRQ(EVENTROUTER_IRQn);
+
+            // Configure RTC wakeup interval
+            if (valid_mask != 0 || detect) {
+                rtc_wakeup(60);
+            } else {
+                rtc_wakeup(3);
+            }
+
+            LPC_RTC->ILR = 3;
+            LPC_EVENTROUTER->CLR_STAT = 0xFFFFFFFF;
+            NVIC_ClearPendingIRQ(RTC_IRQn);
+            NVIC_ClearPendingIRQ(EVENTROUTER_IRQn);
+
+            __disable_irq();
+
+            // Configure and enter Deep Sleep
+            SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+
+            __DSB();
+            __ISB();
+
+            // CPU enters sleep here
+            __WFI();
+
+            // --- WAKEUP SEQUENCE ---
+            __enable_irq();
+            SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+
+            // Cleanup RTC and restore peripheral clocks
+            LPC_RTC->AMR = 0xFF;
+            LPC_RTC->ILR = 3;
+            LPC_CGU->BASE_APB1_CLK.PD = 0;
+            LPC_RGU->RESET_CTRL[1] = (1 << 16);
+
+            // Short delay for power stability (3V3 rail)
+            for (volatile int d = 0; d < 10000; d++);
+
+            // Restart I2C controller
+            LPC_CGU->BASE_APB1_CLK.PD = 0;
+            portapack::i2c0.start(i2c_config_12mhz);
+
+            // Restore original interrupt enable states
+            NVIC->ISER[0] = saved_iser0;
+            NVIC->ISER[1] = saved_iser1;
+            NVIC->ISER[2] = saved_iser2;
+
+        }  // End of while(1) deep sleep loop
+    } else {
+        portapack::display.wake(true);
+    }
+}
+
 eventmask_t EventDispatcher::wait() {
     return chEvtWaitAny(ALL_EVENTS);
 }

firmware/application/event_m0.hpp

@@ -63,6 +63,8 @@ class EventDispatcher {
 
     static void set_display_sleep(const bool sleep);
 
+    static void charge_deep_sleep(const bool sleep);
+
     static inline void check_fifo_isr() {
         if (!shared_memory.application_queue.is_empty()) {
             events_flag_isr(EVT_MASK_APPLICATION);

firmware/application/external/sdusb/ui_sd_over_usb.cpp

@@ -45,7 +45,7 @@ SdOverUsbView::SdOverUsbView(NavigationView& nav)
         sdcDisconnect(&SDCD1);
         sdcStop(&SDCD1);
 
-        portapack::shutdown(true);
+        portapack::shutdown(true, false);
         baseband::run_prepared_image(portapack::memory::map::m4_code.base());
         m0_halt();
         /* will not return*/

firmware/application/hw/rffc507x_spi.cpp

@@ -103,5 +103,13 @@ data_t SPI::transfer_word(const Direction direction, const address_t address, co
     return data_in;
 }
 
+void SPI::power_down() {
+    // A 0x01 address the MIX_CTRL register. A 0x0000
+    transfer_word(Direction::Write, 0x01, 0x0000);
+
+    // a chip 300 µA-es Power Down
+    transfer_word(Direction::Write, 0x00, 0x0000);
+}
+
 }  // namespace spi
 }  // namespace rffc507x

firmware/application/hw/rffc507x_spi.hpp

@@ -41,6 +41,7 @@ class SPI {
     };
 
     void init();
+    void power_down();
 
     reg_t read(const address_t address) {
         return transfer_word(Direction::Read, address, 0);

firmware/application/irq_rtc.cpp

@@ -27,6 +27,8 @@
 using namespace lpc43xx;
 
 #include "event_m0.hpp"
+#include "nvic.h"
+#include "lpc43xx.inc"
 
 static Thread* thread_rtc_event = NULL;
 
@@ -36,6 +38,84 @@ void rtc_interrupt_enable() {
     nvicEnableVector(RTC_IRQn, CORTEX_PRIORITY_MASK(LPC_RTC_IRQ_PRIORITY));
 }
 
+void rtc_reset_default() {
+    // 1. FULL RTC CLEANUP/RESET
+    LPC_RTC->CIIR = 0;
+    LPC_RTC->AMR = 0xFF;  // Disable all alarms
+    LPC_RTC->ILR = 3;     // Clear stuck interrupt flags
+    LPC_RTC->ASEC = 0;
+    LPC_RTC->AMIN = 0;
+    LPC_RTC->AHRS = 0;
+
+    // 2. RESET EVENT ROUTER
+    // Reset to edge-triggered (Garantálja, hogy nem ragad be az ébresztés!)
+    LPC_EVENTROUTER->EDGE |= (1 << 5);
+
+    // DISABLE RTC channel routing
+    LPC_EVENTROUTER->CLR_EN = (1 << 5);
+
+    // Clear pending events
+    LPC_EVENTROUTER->CLR_STAT = 0xFFFFFFFF;
+}
+
+void rtc_wakeup_init() {
+    rtc_reset_default();
+
+    // 1. Force RTC Clock (In case it was modified by the app)
+    // Bit 0: Enable, Bit 4: Calibration OFF
+    LPC_RTC->CCR = (1 << 0);
+
+    // 2. EVENT ROUTER CONFIGURATION
+    LPC_EVENTROUTER->HILO |= (1 << 5);
+    LPC_EVENTROUTER->EDGE |= (1 << 5);       // <-- JAVÍTVA! (Itt volt a hiba a te kódodban)
+    LPC_EVENTROUTER->CLR_STAT = 0xFFFFFFFF;  // Clear pending events
+    LPC_EVENTROUTER->SET_EN = (1 << 5);      // Enable RTC channel routing
+
+    // 3. NVIC Cleanup
+    NVIC_ClearPendingIRQ(RTC_IRQn);
+    NVIC_ClearPendingIRQ(EVENTROUTER_IRQn);
+    NVIC_EnableIRQ(RTC_IRQn);
+    NVIC_EnableIRQ(EVENTROUTER_IRQn);
+}
+
+void rtc_wakeup(uint32_t sleep_seconds) {
+    // 1. Safety cleanup after application tasks
+    LPC_RTC->CCR &= ~(1 << 4);  // Disable calibration (Important!)
+
+    uint32_t sec = LPC_RTC->SEC;
+    uint32_t min = LPC_RTC->MIN;
+    uint32_t hrs = LPC_RTC->HRS;
+
+    sec += sleep_seconds;
+    while (sec >= 60) {
+        sec -= 60;
+        min++;
+    }
+    while (min >= 60) {
+        min -= 60;
+        hrs++;
+    }
+    while (hrs >= 24) {
+        hrs -= 24;
+    }
+
+    // 2. Write values to alarm registers
+    LPC_RTC->ASEC = sec;
+    LPC_RTC->AMIN = min;
+    LPC_RTC->AHRS = hrs;
+
+    // Mask for SEC, MIN, HRS (Disable all other alarm triggers)
+    uint32_t mask = 0xFF ^ ((1 << 0) | (1 << 1) | (1 << 2));
+    LPC_RTC->AMR = mask;
+
+    // Verify write (Sync with RTC domain)
+    while (LPC_RTC->ASEC != sec);
+    while (LPC_RTC->AMR != mask);
+
+    // Brief extra delay to allow internal logic to settle/latch
+    for (volatile int i = 0; i < 5000; i++) __asm__("nop");
+}
+
 extern "C" {
 
 CH_IRQ_HANDLER(RTC_IRQHandler) {

firmware/application/irq_rtc.hpp

@@ -22,6 +22,11 @@
 #ifndef __IPC_RTC_H__
 #define __IPC_RTC_H__
 
+#include <cstdint>
+
 void rtc_interrupt_enable();
+void rtc_reset_default();
+void rtc_wakeup_init();
+void rtc_wakeup(uint32_t sleep_seconds);
 
 #endif /*__IPC_RTC_H__*/

firmware/application/main.cpp

@@ -141,6 +141,8 @@ Continuous (Fox-oring)
 #include <string.h>
 #include "i2cdevmanager.hpp"
 
+#include "lpc43xx.inc"
+
 #include "rffc507x.hpp" /* c/m, avoiding initial short ON Ant_DC_Bias pulse, from cold reset  */
 rffc507x::RFFC507x first_if;
 ui::SystemView* system_view_ptr;
@@ -181,6 +183,8 @@ static void event_loop() {
 }
 
 int main(void) {
+    rtc_reset_default();
+
 #ifndef PRALINE      // Do not perform quick set up of GP01_RFF507X = 1 for PRALINE
     first_if.init(); /* To avoid initial short Ant_DC_Bias pulse ,we need quick set up GP01_RFF507X =1 */
 #endif

firmware/application/portapack.cpp

@@ -339,6 +339,20 @@ static void shutdown_base() {
     clock_manager.shutdown();
 }
 
+static void shutdown_base_12mhz() {
+    i2c0.stop();
+
+    set_clock_config(clock_config_irc);
+
+    cgu::pll1::disable();
+
+    set_idivc_base_clocks(cgu::CLK_SEL::IRC);
+
+    i2c0.start(i2c_config_boot_clock);
+
+    clock_manager.shutdown();
+}
+
 static void set_cpu_clock_speed() {
     /* Incantation from LPC43xx UM10503 section 12.2.1.1, to bring the M4
      * core clock speed to the 110 - 204MHz range.
@@ -698,7 +712,7 @@ init_status_t init() {
     return return_code;
 }
 
-void shutdown(const bool leave_screen_on) {
+void shutdown(const bool leave_screen_on, const bool slow_clock) {
     gpdma::controller.disable();
 
     if (!leave_screen_on) {
@@ -712,8 +726,12 @@ void shutdown(const bool leave_screen_on) {
 
     hackrf::cpld::init_from_eeprom();
 
+    if (slow_clock) {
+        shutdown_base_12mhz();
+    } else {
         shutdown_base();
     }
+}
 
 void setEventDispatcherToUSBSerial(EventDispatcher* evt) {
     usb_serial.setEventDispatcher(evt);

firmware/application/portapack.hpp

@@ -78,7 +78,7 @@ void set_antenna_bias(const bool v);
 bool get_antenna_bias();
 
 init_status_t init();
-void shutdown(const bool leave_screen_on = false);
+void shutdown(const bool leave_screen_on = false, const bool slow_clock = false);
 
 void setEventDispatcherToUSBSerial(EventDispatcher* evt);
 

firmware/application/ui_navigation.cpp

@@ -347,11 +347,11 @@ void SystemStatusView::on_battery_data(const BatteryStateMessage* msg) {
         // Only show charging modal when transitioning to charging state
         nav_.display_modal(
             "CHARGING",
-            "Screen on while charging?",
+            "Enter deep sleep? \n \nExit: Press reset button. \n \nRX LED: Charging. \nTX LED: Charging error. \nLEDs OFF: Charge complete.",
             YESNO,
-            [this](bool keep_screen_on) {
+            [this](bool deepsleep) {
-                if (!keep_screen_on) {
+                if (deepsleep) {
-                    EventDispatcher::set_display_sleep(true);
+                    EventDispatcher::charge_deep_sleep(true);
                 }
             });
     }

firmware/chibios-portapack/boards/PORTAPACK_APPLICATION/board.cpp

@@ -15,7 +15,6 @@
     limitations under the License.
 */
 
-
 #include "ch.h"
 #include "hal.h"
 
@@ -52,7 +51,8 @@ bool hackrf_r9;
  */
 const PALConfig pal_default_config = {
     .P = {
-    {   // GPIO0
+        {
+            // GPIO0
             .data
 #ifdef PRALINE
             = (0 << 15)  // P1_20: CLKIN_CTRL - start low
@@ -97,9 +97,9 @@ const PALConfig pal_default_config = {
               | (0 << 1)   // P0_1:  SGPIO1, HOST_DATA1
               | (0 << 0)   // P0_0:  SGPIO0, HOST_DATA0
         },
-    {   // GPIO1
+        {
-        .data
+            // GPIO1
-            = (1 << 15) // P3_5:  SPIFI_SIO2
+            .data = (1 << 15)    // P3_5:  SPIFI_SIO2
                     | (1 << 14)  // P3_4:  SPIFI_SIO3
                     | (1 << 13)  // P2_13: PortaPack DIR
                     | (1 << 12)  // P2_12: !RX_AMP_PWR
@@ -116,8 +116,7 @@ const PALConfig pal_default_config = {
                     | (1 << 1)   // P1_8:  PortaPack CPLD.TMS(I)
                     | (0 << 0)   // P1_7:  !MIX_BYPASS
             ,
-        .dir
+            .dir = (0 << 15)    // P3_5:  SPIFI_SIO2
-            = (0 << 15) // P3_5:  SPIFI_SIO2
                    | (0 << 14)  // P3_4:  SPIFI_SIO3
                    | (0 << 13)  // P2_13: PortaPack DIR
                    | (1 << 12)  // P2_12: !RX_AMP_PWR
@@ -134,9 +133,9 @@ const PALConfig pal_default_config = {
                    | (0 << 1)   // P1_8:  PortaPack CPLD.TMS(I) (output only when needed, pull up internal to CPLD)
                    | (1 << 0)   // P1_7:  !MIX_BYPASS
         },
-    {   // GPIO2
+        {
-        .data
+            // GPIO2
-            = (0 << 15) // P5_6:  TX_AMP
+            .data = (0 << 15)    // P5_6:  TX_AMP
                     | (1 << 14)  // P5_5:  MIXER_RESETX, 10K PU
 #ifdef PRALINE
                     | (0 << 13)  // P5_4:  MIXER_ENX, 10K PU
@@ -157,8 +156,7 @@ const PALConfig pal_default_config = {
                     | (0 << 1)   // P4_1:  LED1 (USB)
                     | (1 << 0)   // P4_0:  HP
             ,
-        .dir
+            .dir = (1 << 15)  // P5_6:  TX_AMP
-            = (1 << 15) // P5_6:  TX_AMP
 #ifdef PRALINE
                    | (0 << 14)  // P5_5:  MIXER_RESETX, 10K PU
                    | (1 << 13)  // P5_4:  MIXER_ENX - OUTPUT (MCU controlled)
@@ -183,9 +181,9 @@ const PALConfig pal_default_config = {
                    | (1 << 1)  // P4_1:  LED1 (USB)
                    | (1 << 0)  // P4_0:  HP
         },
-    {   // GPIO3
+        {
-        .data
+            // GPIO3
-            = (1 << 15) // P7_7:  PortaPack GPIO3_15(IO)
+            .data = (1 << 15)    // P7_7:  PortaPack GPIO3_15(IO)
                     | (1 << 14)  // P7_6:  PortaPack GPIO3_14(IO)
                     | (1 << 13)  // P7_5:  PortaPack GPIO3_13(IO)
                     | (1 << 12)  // P7_4:  PortaPack GPIO3_12(IO)
@@ -202,8 +200,7 @@ const PALConfig pal_default_config = {
                     | (1 << 1)   // P6_2:  HackRF CPLD.TDI(I), PortaPack I2S0_RX_SDA(O), PortaPack CPLD.TDI(I) (output only when needed, pull-up internal to CPLD when 1V8 present)
                     | (1 << 0)   // P6_1:  HackRF CPLD.TCK(I), PortaPack CPLD.TCK(I) (output only when needed, pull-up internal to CPLD when 1V8 present)
             ,
-        .dir
+            .dir = (0 << 15)    // P7_7:  PortaPack GPIO3_15(IO)
-            = (0 << 15) // P7_7:  PortaPack GPIO3_15(IO)
                    | (0 << 14)  // P7_6:  PortaPack GPIO3_14(IO)
                    | (0 << 13)  // P7_5:  PortaPack GPIO3_13(IO)
                    | (0 << 12)  // P7_4:  PortaPack GPIO3_12(IO)
@@ -220,16 +217,15 @@ const PALConfig pal_default_config = {
                    | (0 << 1)   // P6_2:  HackRF CPLD.TDI(I), PortaPack I2S0_RX_SDA(O), PortaPack CPLD.TDI(I) (output only when needed, pull-up internal to CPLD when 1V8 present)
                    | (0 << 0)   // P6_1:  HackRF CPLD.TCK(I), PortaPack CPLD.TCK(I) (output only when needed, pull-up internal to CPLD when 1V8 present)
         },
-    {   // GPIO4
+        {
-        .data
+            // GPIO4
-            = (1 << 11) // P9_6:  SGPIO8, SGPIO_CLK
+            .data = (1 << 11)  // P9_6:  SGPIO8, SGPIO_CLK
             ,
-        .dir
+            .dir = (0 << 11)  // P9_6:  SGPIO8, SGPIO_CLK
-            = (0 << 11) // P9_6:  SGPIO8, SGPIO_CLK
         },
-    {   // GPIO5
+        {
-        .data
+            // GPIO5
-            = (1 << 18) // P9:5:  HackRF CPLD.TDO(O) (input with pull up)
+            .data = (1 << 18)    // P9:5:  HackRF CPLD.TDO(O) (input with pull up)
                     | (1 << 16)  // P6_8:  MIX_BYPASS
                     | (0 << 15)  // P6_7:  Varies by revision, float until detection
                     | (1 << 14)  // P4_10: SGPIO15, CPLD (unused)
@@ -248,8 +244,7 @@ const PALConfig pal_default_config = {
                     | (0 << 1)   // P2_1:  PortaPack ADDR
                     | (1 << 0)   // P2_0:  PortaPack IO_STBX
             ,
-        .dir
+            .dir = (0 << 18)    // P9_5:  HackRF CPLD.TDO(O) (input with pull up)
-            = (0 << 18) // P9_5:  HackRF CPLD.TDO(O) (input with pull up)
                    | (1 << 16)  // P6_8:  MIX_BYPASS
                    | (0 << 15)  // P6_7:  Varies by revision, float until detection
                    | (0 << 14)  // P4_10: SGPIO15, CPLD (unused)
@@ -270,12 +265,10 @@ const PALConfig pal_default_config = {
         },
         {// GPIO6
          .data = 0,
-        .dir = 0
+         .dir = 0},
-    },
         {// GPIO7
          .data = 0,
-        .dir = 0
+         .dir = 0},
-    },
     },
     .SCU = {
         /* Configure GP_CLKIN as soon as possible. It's an output at boot time, and the Si5351C doesn't
@@ -310,8 +303,7 @@ const PALConfig pal_default_config = {
              .sda_ehd = 0,  // SDA: Standard/Fast mode
              .sda_ezi = 1,  // SDA: Input enabled
              .sda_zif = 0   // SDA: Enable input glitch filter
-        }
+         }},
-    },
 
         /* Radio section control */
         {1, 3, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}},  /* SSP1_MISO/P41: MAX2837.DOUT(O) */
@@ -395,54 +387,47 @@ const PALConfig pal_default_config = {
         {5, 0, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}},
         {6, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}},
         {6, 10, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}},
-  }
+    }};
-};
 
 /* Additional GPIO configuration for HackRF OG */
 static const std::array<gpio_setup_t, 6> gpio_setup_og{{
-    {   // GPIO0
+    {
-        .data
+        // GPIO0
-            = (0 <<  9) // P1_2:  10K PD, BOOT1
+        .data = (0 << 9)    // P1_2:  10K PD, BOOT1
                 | (1 << 8)  // P1_1:  10K PU, BOOT0
                 | (1 << 7)  // P2_7:  10K PU, ISP
         ,
-        .dir
+        .dir = (0 << 9)    // P1_2:  10K PD, BOOT1
-            = (0 <<  9) // P1_2:  10K PD, BOOT1
                | (0 << 8)  // P1_1:  10K PU, BOOT0
                | (0 << 7)  // P2_7:  10K PU, ISP
     },
     {// GPIO1
      .data = 0,
-        .dir = 0
+     .dir = 0},
-    },
+    {
-    {   // GPIO2
+        // GPIO2
-        .data
+        .data = (1 << 9)    // P5_0:  !VAA_ENABLE
-            = (1 <<  9) // P5_0:  !VAA_ENABLE
                 | (0 << 4)  // P4_4:  TXENABLE
         ,
-        .dir
+        .dir = (1 << 9)    // P5_0:  !VAA_ENABLE
-            = (1 <<  9) // P5_0:  !VAA_ENABLE
                | (1 << 4)  // P4_4:  TXENABLE
     },
-    {   // GPIO3
+    {
-        .data
+        // GPIO3
-            = (0 <<  6) // P6_10: EN1V8, 10K PD
+        .data = (0 << 6)  // P6_10: EN1V8, 10K PD
         ,
-        .dir
+        .dir = (1 << 6)  // P6_10: EN1V8, 10K PD
-            = (1 <<  6) // P6_10: EN1V8, 10K PD
     },
     {// GPIO4
      .data = 0,
-        .dir = 0
+     .dir = 0},
-    },
+    {
-    {   // GPIO5
+        // GPIO5
-        .data
+        .data = (0 << 15)    // P6_7:  TX
-            = (0 << 15) // P6_7:  TX
                 | (0 << 12)  // P4_8:  SGPIO13, HOST_SYNC_EN
                 | (1 << 5)   // P2_5:  RX
         ,
-        .dir
+        .dir = (1 << 15)    // P6_7:  TX
-            = (1 << 15) // P6_7:  TX
                | (0 << 12)  // P4_8:  SGPIO13, HOST_SYNC_EN
                | (1 << 5)   // P2_5:  RX
     },
@@ -450,49 +435,43 @@ static const std::array<gpio_setup_t, 6> gpio_setup_og { {
 
 /* Additional GPIO configuration for HackRF r9 */
 static const std::array<gpio_setup_t, 6> gpio_setup_r9{{
-    {   // GPIO0
+    {
-        .data
+        // GPIO0
-            = (0 <<  9) // P1_2:  10K PD, BOOT1, CLKOUT_EN
+        .data = (0 << 9)    // P1_2:  10K PD, BOOT1, CLKOUT_EN
                 | (1 << 8)  // P1_1:  10K PU, BOOT0, MCU_CLK_EN
                 | (1 << 7)  // P2_7:  10K PU, ISP, RX
         ,
-        .dir
+        .dir = (0 << 9)    // P1_2:  10K PD, BOOT1, CLKOUT_EN
-            = (0 <<  9) // P1_2:  10K PD, BOOT1, CLKOUT_EN
                | (0 << 8)  // P1_1:  10K PU, BOOT0, MCU_CLK_EN
                | (0 << 7)  // P2_7:  10K PU, ISP, RX
     },
     {// GPIO1
      .data = 0,
-        .dir = 0
+     .dir = 0},
-    },
+    {
-    {   // GPIO2
+        // GPIO2
-        .data
+        .data = (1 << 9)    // P5_0:  EN1V8, 10K PD
-            = (1 <<  9) // P5_0:  EN1V8, 10K PD
                 | (1 << 4)  // P4_4:  !ANT_BIAS
         ,
-        .dir
+        .dir = (1 << 9)    // P5_0:  EN1V8, 10K PD
-            = (1 <<  9) // P5_0:  EN1V8, 10K PD
                | (1 << 4)  // P4_4:  !ANT_BIAS
     },
-    {   // GPIO3
+    {
-        .data
+        // GPIO3
-            = (1 <<  6) // P6_10: !VAA_ENABLE
+        .data = (1 << 6)  // P6_10: !VAA_ENABLE
         ,
-        .dir
+        .dir = (1 << 6)  // P6_10: !VAA_ENABLE
-            = (1 <<  6) // P6_10: !VAA_ENABLE
     },
     {// GPIO4
      .data = 0,
-        .dir = 0
+     .dir = 0},
-    },
+    {
-    {   // GPIO5
+        // GPIO5
-        .data
+        .data = (0 << 15)    // P6_7:  CLKIN_EN
-            = (0 << 15) // P6_7:  CLKIN_EN
                 | (0 << 12)  // P4_8:  CLKIN_DETECT
                 | (0 << 5)   // P2_5:  HOST_SYNC_EN
         ,
-        .dir
+        .dir = (1 << 15)    // P6_7:  CLKIN_EN
-            = (1 << 15) // P6_7:  CLKIN_EN
                | (0 << 12)  // P4_8:  CLKIN_DETECT
                | (0 << 5)   // P2_5:  HOST_SYNC_EN
     },
@@ -763,7 +742,10 @@ void vaa_power_on(void) {
         /* Timing assumes we're running immediately after the bootloader: 96 MHz from IRC+PLL1
          */
         while (enable_period < cycle_period) {
-      { volatile uint32_t delay = 2000; while(delay--); }
+            {
+                volatile uint32_t delay = 2000;
+                while (delay--);
+            }
             enable_period <<= 1;
             LPC_MCPWM->MAT2 = cycle_period - enable_period;
         }
@@ -919,19 +901,28 @@ extern "C" void boardInit(void) {
     LPC_SCU->SFSP[6][7] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
     LPC_GPIO->DIR[5] |= (1 << 15);
     LPC_GPIO->CLR[5] = (1 << 15); /* Clear = enable 3.3V aux */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* Enable 1.2V for FPGA - P8_7 = GPIO4[7], active high */
     LPC_SCU->SFSP[8][7] = 0x10;
     LPC_GPIO->DIR[4] |= (1 << 7);
     LPC_GPIO->SET[4] = (1 << 7);
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* Enable VAA for RF - P8_1 = GPIO4[1], active low */
     LPC_SCU->SFSP[8][1] = 0x10;
     LPC_GPIO->DIR[4] |= (1 << 1);
     LPC_GPIO->CLR[4] = (1 << 1);
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* Configure RFFC5072 pins for PRALINE */
     /* Set GPIO directions for RFFC5072 SPI pins */
@@ -950,7 +941,10 @@ extern "C" void boardInit(void) {
     /* SCU configured in PAL array above with mode=4 */
     LPC_GPIO->CLR[5] = (1 << 6);  /* Default low (mixer enabled) */
     LPC_GPIO->DIR[5] |= (1 << 6); /* Output */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* Configure Port D pins for PRALINE (use SFSPD registers) */
     /* PD_14 = GPIO6[28] MAX2831 chip select */
@@ -967,7 +961,10 @@ extern "C" void boardInit(void) {
     LPC_SCU->SFSPD[16] = 0xF4;     /* SCU_GPIO_FAST | FUNCTION4 */
     LPC_GPIO->SET[6] |= (1 << 30); /* CS high (inactive) */
     LPC_GPIO->DIR[6] |= (1 << 30); /* Output */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* Configure Port E pins for MAX2831 control (use SFSPE registers) */
     /* PE_1 = GPIO7[1] MAX2831 ENABLE */
@@ -978,7 +975,10 @@ extern "C" void boardInit(void) {
     LPC_SCU->SFSPE[2] = 0xF4;     /* SCU_GPIO_FAST | FUNCTION4 */
     LPC_GPIO->CLR[7] = (1 << 2);  /* Start in shutdown mode */
     LPC_GPIO->DIR[7] |= (1 << 2); /* Output */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* Configure Port 6 pins for RF path control */
     /* P6_3 = GPIO3[2] Mixer enable (inverted: 0 = mixer ON) */
@@ -989,7 +989,10 @@ extern "C" void boardInit(void) {
     LPC_SCU->SFSP[6][5] = 0xF0;   /* SCU_GPIO_FAST | FUNCTION0 */
     LPC_GPIO->CLR[3] = (1 << 4);  /* TX off by default (RX mode) */
     LPC_GPIO->DIR[3] |= (1 << 4); /* Output */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* Configure Port A pins for RF path control */
     /* PA_1 = GPIO4[8] LPF enable */
@@ -1000,20 +1003,29 @@ extern "C" void boardInit(void) {
     LPC_SCU->SFSP[0xA][2] = 0xF0; /* SCU_GPIO_FAST | FUNCTION0 */
     LPC_GPIO->CLR[4] = (1 << 9);  /* RF amp off by default */
     LPC_GPIO->DIR[4] |= (1 << 9); /* Output */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* Configure RFFC5072 control pins for PRALINE */
     /* P5_4 = GPIO2[13] RFFC5072 ENX - SPI chip select (managed by SPI driver) */
     LPC_SCU->SFSP[5][4] = 0x10;    /* FUNCTION0 (GPIO), pull-up, slow mode (matches HackRF USB) */
     LPC_GPIO->DIR[2] |= (1 << 13); /* ENX: OUTPUT */
     LPC_GPIO->SET[2] = (1 << 13);  /* ENX = 1 (deselected initially) */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* P5_5 = GPIO2[14] RFFC5072 RESETX (active high: 1=running) */
     LPC_SCU->SFSP[5][5] = 0x10;    /* FUNCTION0 (GPIO), pull-up, slow mode (matches HackRF USB) */
     LPC_GPIO->DIR[2] |= (1 << 14); /* RESETX: OUTPUT */
     LPC_GPIO->SET[2] = (1 << 14);  /* RESETX = 1 (RUNNING) */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* Ensure RESETX is stable */
     for (volatile int i = 0; i < 10; i++) {
@@ -1023,7 +1035,10 @@ extern "C" void boardInit(void) {
     /* PD_11 = GPIO6[25] RFFC5072 Lock Detect (input) */
     LPC_SCU->SFSPD[11] = 0x10;      /* FUNCTION0 (GPIO), pull-up (matches HackRF USB) */
     LPC_GPIO->DIR[6] &= ~(1 << 25); /* LD: INPUT */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* Configure PRALINE-specific SGPIO pins for FPGA sample interface.
      * These override the HackRF One pin config from pins_setup.
@@ -1043,7 +1058,10 @@ extern "C" void boardInit(void) {
     LPC_SCU->SFSP[8][2] = 0xF4; /* SCU_GPIO_FAST | func 4 */
     /* SGPIO11 = P1_17 function 6 (HOST_DIRECTION - output to FPGA, tells FPGA TX vs RX) */
     LPC_SCU->SFSP[1][17] = 0xF6; /* SCU_GPIO_FAST | func 6 */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     /* SGPIO data pins (SGPIO0-7) - all 8 bits required for sample data */
     LPC_SCU->SFSP[0][0] = 0xF3;  /* SGPIO0: P0_0 function 3, HOST_DATA0 */
@@ -1054,7 +1072,10 @@ extern "C" void boardInit(void) {
     LPC_SCU->SFSP[6][6] = 0xF2; /* SGPIO5: P6_6 function 2, HOST_DATA5 */
     LPC_SCU->SFSP[2][2] = 0xF0; /* SGPIO6: P2_2 function 0, HOST_DATA6 */
     LPC_SCU->SFSP[1][0] = 0xF6; /* SGPIO7: P1_0 function 6, HOST_DATA7 */
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
     // Trigger FPGA bitstream loading via fpga bridge in portapack.cpp
     // Use LEDs to check if boardInit initialization is successful.
@@ -1066,7 +1087,10 @@ extern "C" void boardInit(void) {
     // Turn off all LEDs to start
     // PRALINE LEDs are active-low: SET (HIGH) = OFF, CLR (LOW) = ON
     LPC_GPIO->SET[2] = (1 << 1) | (1 << 2) | (1 << 8);
-  { volatile uint32_t delay = 200000; while(delay--); }
+    {
+        volatile uint32_t delay = 200000;
+        while (delay--);
+    }
 
 #else
 
@@ -1095,7 +1119,6 @@ extern "C" void boardInit(void) {
     }
 
 #endif
-
 }
 
 extern "C" void _default_exit(void) {

firmware/chibios-portapack/os/hal/platforms/LPC43xx/lpc43xx.inc

@@ -1167,6 +1167,21 @@ typedef struct {
   __IO uint32_t AYRS;
 } LPC_RTC_Type;
 
+// ------------------------------------------------------------------------------------------------
+// -----                                         EVENT ROUTER                                 -----
+// ------------------------------------------------------------------------------------------------
+
+typedef struct {
+  __IO uint32_t HILO;       /* +0x000 */
+  __IO uint32_t EDGE;       /* +0x004 */
+  __O  uint32_t CLR_EN;     /* +0x008 */
+  __O  uint32_t SET_EN;     /* +0x00C */
+  __I  uint32_t STATUS;     /* +0x010 */
+  __I  uint32_t ENABLE;     /* +0x014 */
+  __O  uint32_t CLR_STAT;   /* +0x018 */
+  __O  uint32_t SET_STAT;   /* +0x01C */
+} LPC_EVENTROUTER_Type;
+
 // ------------------------------------------------------------------------------------------------
 // -----                                       USART0/2/3                                     -----
 // ------------------------------------------------------------------------------------------------
@@ -1466,6 +1481,7 @@ typedef struct {
 #define LPC_ADC1                  ((LPC_ADCx_Type           *) LPC_ADC1_BASE)
 #define LPC_GPIO                  ((LPC_GPIO_Type           *) LPC_GPIO_BASE)
 #define LPC_SGPIO                 ((LPC_SGPIO_Type          *) LPC_SGPIO_BASE)
+#define LPC_EVENTROUTER           ((LPC_EVENTROUTER_Type *) LPC_EVENT_ROUTER_BASE)
 
 #ifdef __cplusplus
 }

firmware/common/hackrf_gpio.hpp

@@ -128,7 +128,8 @@ constexpr GPIO gpio_q_invert = gpio[GPIO0_13];
 constexpr GPIO gpio_vaa_disable = gpio[GPIO4_1];      // VAA disable (P8_1)
 constexpr GPIO gpio_1v2_enable = gpio[GPIO4_7];       // 1V2 enable (P8_7)
 constexpr GPIO gpio_3v3aux_disable = gpio[GPIO5_15];  // 3V3 aux disable (P6_7)
-
+constexpr GPIO gpio_vbus_enable = gpio[GPIO8_4];      // VBUS_IN_EN P8_4 ->LOW
+constexpr GPIO gpio_vin_enable = gpio[GPIO8_5];       // VIN_IN_EN P8_5 ->HIGH
 // PRALINE RF path control
 constexpr GPIO gpio_tx_enable = gpio[GPIO3_4];  // TX enable (P6_5)
 // constexpr GPIO gpio_mix_enable_n = gpio[GPIO3_2];       // Mixer enable inverted (P6_3)

firmware/common/i2cdev_ppmod.cpp

@@ -246,7 +246,9 @@ bool I2cDev_PPmod::send_poweroff_command() {
     if (isLocked()) return false;  // device is busy
     Command cmd = Command::COMMAND_POWER_OFF;
     uint8_t tmp = 0;  // result of the ack. 0 = no, 1 = ok
-    i2c_read((uint8_t*)&cmd, 2, &tmp, 1);
+    if (!i2c_read((uint8_t*)&cmd, 2, &tmp, 1)) {
+        return false;
+    }
     return (tmp == 1);
 }
 

firmware/common/pins.hpp

@@ -115,7 +115,9 @@ enum Pins {
     PA_1,
     PA_2,
     // Port 8 pins (PRALINE power control and LED4)
-    P8_1,
+    P8_1,  // VAA_EN
+    P8_4,  // VBUS_IN_EN
+    P8_5,  // VIN_IN_EN
     P8_6,
     P8_7,
     // Port E pins (PRALINE transceiver control)
@@ -227,6 +229,8 @@ constexpr Pin pins[]{
     [PA_2] = {0xA, 2},
     // Port 8 pins
     [P8_1] = {8, 1},
+    [P8_4] = {8, 4},
+    [P8_5] = {8, 5},
     [P8_6] = {8, 6},
     [P8_7] = {8, 7},
     // Port E pins (function 4 = GPIO)
@@ -333,6 +337,8 @@ enum GPIOs {
     GPIO4_14,
     // Power control and LED4
     GPIO4_1,
+    GPIO8_4,
+    GPIO8_5,
     GPIO4_6,
     GPIO4_7,
     // RF path control
@@ -445,6 +451,8 @@ constexpr GPIO gpio[] = {
 #ifdef PRALINE
     [GPIO4_14] = {pins[P9_2], 4, 14, 0},   // RFFC5072 mixer data
     [GPIO4_1] = {pins[P8_1], 4, 1, 0},     // VAA disable
+    [GPIO8_4] = {pins[P8_4], 8, 4, 0},     // VBUS_IN_EN
+    [GPIO8_5] = {pins[P8_5], 8, 5, 0},     // VIN_IN_EN
     [GPIO4_6] = {pins[P8_6], 4, 6, 0},     // LED4
     [GPIO4_7] = {pins[P8_7], 4, 7, 0},     // 1V2 enable
     [GPIO4_8] = {pins[PA_1], 4, 8, 0},     // LPF enable
@@ -462,6 +470,8 @@ constexpr GPIO gpio[] = {
     // Placeholder entries for non-PRALINE builds (use P0_0 as dummy)
     [GPIO4_14] = {pins[P0_0], 4, 14, 0},
     [GPIO4_1] = {pins[P0_0], 4, 1, 0},
+    [GPIO8_4] = {pins[P0_0], 8, 4, 0},
+    [GPIO8_5] = {pins[P0_0], 8, 5, 0},
     [GPIO4_6] = {pins[P0_0], 4, 6, 0},
     [GPIO4_7] = {pins[P0_0], 4, 7, 0},
     [GPIO4_8] = {pins[P0_0], 4, 8, 0},