mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-09-13 01:59:29 +00:00
Add praline gpio (#3218)
* Implement antenna bias control for Praline and update GPIO configurations * Add GPIO power management functions and update board initialization for Praline * Refactor power management functions for Praline and update GPIO configurations * Update GPIO configurations for Praline and enable power control pins. AA_EN enabled * Refactor GPIO configuration for Praline: update array size definitions and clean up comments * Add P1 and P2 control functions for PRALINE * Introduced P1_Function and P2_Function enums in ClockManager to manage multiplexer control. * mplemented set_p1_control and set_p2_control methods for configuring P1 and P2 control pins based on specified functions. * Updated clock_manager.hpp and clock_manager.cpp to include new functionality. * Modified MAX2837 and MAX2839 initialization to conditionally configure GPIO based on PRALINE. * Adjusted RFFC507x and RFFC507x_SPI initialization to include GPIO setup for PRALINE. - Refactored RF path initialization to remove unnecessary GPIO setup. - Updated board configuration for PRALINE to reflect new GPIO settings and pin configurations. - Cleaned up FPGA bridge code by removing unused pin configuration functions. - Adjusted SCU array size in pal_lld.h for PRALINE. - Enhanced hackrf_gpio.hpp to define multiplexer control pins for PRALINE. - Modified LED setup to accommodate active-low configuration for PRALINE. * Refactor GPIO and power control functions - Removed unused power control function declarations from board.h. - Enhanced gpio.hpp with new pin setup functions and GPIO control structures for PRALINE. - Consolidated multiplexer control pin definitions into gpio_control namespace. - Moved power control function implementations to gpio.cpp, including detailed VAA power management logic. - Updated power control functions to handle both PRALINE and HackRF R9 configurations. - Cleaned up hackrf_gpio.hpp by removing redundant multiplexer control definitions. * Refactor GPIO control for PRALINE: update MAX2831 and RFFC507x configurations, add new GPIO mappings * Refactor GPIO configurations for PRALINE: update anti-aliasing filter pin mapping, enhance LED setup logic, and add placeholder GPIO entries. * Refactor GPIO configurations for PRALINE: update LED mappings and remove unused anti-aliasing filter GPIO entry.
This commit is contained in:
Pezsma
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@@ -33,12 +33,10 @@
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#ifdef __cplusplus
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extern "C" {
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#endif
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void boardInit(void);
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void boardInit(void);
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void configure_pins_portapack(void);
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void configure_pins_portapack(void);
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void vaa_power_on(void);
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void vaa_power_off(void);
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#ifdef __cplusplus
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}
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#endif
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@@ -198,34 +198,6 @@ static void ssp1_init_ice40(void) {
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SSP1_CR1_LOCAL = SSP_CR1_SSE;
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}
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// Configure SSP1 pins via SCU
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static void configure_ssp1_pins(void) {
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// P1_3 = SSP1_MISO (function 5)
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MMIO32_LOCAL(SCU_SSP1_CIPO_LOCAL) = SCU_SSP_IO_LOCAL | SCU_CONF_FUNCTION5_LOCAL;
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// P1_4 = SSP1_MOSI (function 5)
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MMIO32_LOCAL(SCU_SSP1_COPI_LOCAL) = SCU_SSP_IO_LOCAL | SCU_CONF_FUNCTION5_LOCAL;
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// P1_19 = SSP1_SCK (function 1)
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MMIO32_LOCAL(SCU_SSP1_SCK_LOCAL) = SCU_SSP_IO_LOCAL | SCU_CONF_FUNCTION1_LOCAL;
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}
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// Configure FPGA control pins via SCU and GPIO
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static void configure_fpga_control_pins(void) {
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// P5_2 = GPIO2[11] = CRESET (function 0, output)
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MMIO32_LOCAL(SCU_FPGA_CRESET_LOCAL) = SCU_GPIO_NOPULL_LOCAL | SCU_CONF_FUNCTION0_LOCAL;
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// P4_10 = GPIO5[14] = CDONE (function 4, input with pullup)
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MMIO32_LOCAL(SCU_FPGA_CDONE_LOCAL) = SCU_GPIO_PUP_LOCAL | SCU_CONF_FUNCTION4_LOCAL;
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// P5_1 = GPIO2[10] = SPI_CS (function 0, output)
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MMIO32_LOCAL(SCU_FPGA_SPI_CS_LOCAL) = SCU_GPIO_NOPULL_LOCAL | SCU_CONF_FUNCTION0_LOCAL;
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// Set CRESET and SPI_CS as outputs (GPIO2[11] and GPIO2[10])
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GPIO_DIR(FPGA_CRESET_PORT) |= (1 << FPGA_CRESET_PIN) | (1 << FPGA_SPI_CS_PIN);
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// Clear both initially
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GPIO_CLR(FPGA_CRESET_PORT) = (1 << FPGA_CRESET_PIN) | (1 << FPGA_SPI_CS_PIN);
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// CDONE is input (GPIO5[14])
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GPIO_DIR(FPGA_CDONE_PORT) &= ~(1 << FPGA_CDONE_PIN);
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}
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// GPIO control helpers
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static void fpga_creset_low(void) {
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GPIO_CLR(FPGA_CRESET_PORT) = (1 << FPGA_CRESET_PIN);
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@@ -578,12 +550,6 @@ int fpga_bridge_init(uint8_t* mem_base) {
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CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_AUTOBLOCK(1) |
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CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1);
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// Configure SSP1 pins
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configure_ssp1_pins();
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// Configure FPGA control pins
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configure_fpga_control_pins();
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// Initialize SSP1 for iCE40 programming
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ssp1_init_ice40();
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@@ -52,8 +52,6 @@
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/* Driver exported functions. */
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/*===========================================================================*/
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#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
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/**
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* @brief LPC43xx I/O ports configuration.
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* @details Ports 0 through 8.
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@@ -62,15 +60,15 @@
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*
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* @notapi
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*/
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void _pal_lld_init(const PALConfig *config) {
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for(size_t i=0; i<8; i++) {
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LPC_GPIO->PIN[i] = config->P[i].data;
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LPC_GPIO->DIR[i] = config->P[i].dir;
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}
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void _pal_lld_init(const PALConfig* config) {
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for (size_t i = 0; i < 8; i++) {
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LPC_GPIO->PIN[i] = config->P[i].data;
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LPC_GPIO->DIR[i] = config->P[i].dir;
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}
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for(size_t i=0; i<ARRAY_SIZE(config->SCU); i++) {
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LPC_SCU->SFSP[config->SCU[i].port][config->SCU[i].pin] = config->SCU[i].config.word;
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}
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for (size_t i = 0; i < SCU_ARRAY_SIZE; i++) {
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LPC_SCU->SFSP[config->SCU[i].port][config->SCU[i].pin] = config->SCU[i].config.word;
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}
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}
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/**
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@@ -87,14 +85,14 @@ void _pal_lld_init(const PALConfig *config) {
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode) {
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/* TODO: Handling pull-up, pull-down modes not implemented, as it would
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* require a map from GPIO to SCU pins. Not today.
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*/
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if( mode == PAL_MODE_OUTPUT_PUSHPULL ) {
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LPC_GPIO->DIR[port] |= mask;
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} else {
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LPC_GPIO->DIR[port] &= ~mask;
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}
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/* TODO: Handling pull-up, pull-down modes not implemented, as it would
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* require a map from GPIO to SCU pins. Not today.
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*/
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if (mode == PAL_MODE_OUTPUT_PUSHPULL) {
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LPC_GPIO->DIR[port] |= mask;
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} else {
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LPC_GPIO->DIR[port] &= ~mask;
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}
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}
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#endif /* HAL_USE_PAL */
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@@ -50,10 +50,18 @@
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* @note Implementations may extend this structure to contain more,
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* architecture dependent, fields.
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*/
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#ifdef PRALINE
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#define SCU_ARRAY_SIZE 78
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#else
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#define SCU_ARRAY_SIZE 56
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#endif
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typedef struct {
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/** @brief GPIO setup data.*/
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gpio_setup_t P[8];
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scu_setup_t SCU[60];
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/** @brief GPIO setup data.*/
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gpio_setup_t P[8];
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scu_setup_t SCU[SCU_ARRAY_SIZE];
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} PALConfig;
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/**
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@@ -94,50 +102,50 @@ typedef uint8_t iopadid_t;
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/**
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* @brief GPIO0 port identifier.
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*/
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#define IOPORT1 0
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#define GPIO0 0
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#define IOPORT1 0
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#define GPIO0 0
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/**
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* @brief GPIO1 port identifier.
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*/
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#define IOPORT2 1
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#define GPIO1 1
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#define IOPORT2 1
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#define GPIO1 1
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/**
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* @brief GPIO1 port identifier.
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*/
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#define IOPORT3 2
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#define GPIO2 2
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#define IOPORT3 2
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#define GPIO2 2
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/**
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* @brief GPIO1 port identifier.
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*/
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#define IOPORT4 3
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#define GPIO3 3
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#define IOPORT4 3
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#define GPIO3 3
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/**
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* @brief GPIO1 port identifier.
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*/
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#define IOPORT5 4
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#define GPIO4 4
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#define IOPORT5 4
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#define GPIO4 4
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/**
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* @brief GPIO1 port identifier.
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*/
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#define IOPORT6 5
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#define GPIO5 5
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#define IOPORT6 5
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#define GPIO5 5
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/**
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* @brief GPIO1 port identifier.
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*/
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#define IOPORT7 6
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#define GPIO6 6
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#define IOPORT7 6
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#define GPIO6 6
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/**
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* @brief GPIO1 port identifier.
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*/
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#define IOPORT8 7
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#define GPIO7 7
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#define IOPORT8 7
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#define GPIO7 7
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/*===========================================================================*/
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/* Implementation, some of the following macros could be implemented as */
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@@ -237,7 +245,7 @@ typedef uint8_t iopadid_t;
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*
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* @notapi
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*/
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//#define pal_lld_readgroup(port, mask, offset) 0
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// #define pal_lld_readgroup(port, mask, offset) 0
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/**
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* @brief Writes a group of bits.
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@@ -253,7 +261,7 @@ typedef uint8_t iopadid_t;
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*
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* @notapi
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*/
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//#define pal_lld_writegroup(port, mask, offset, bits) (void)bits
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// #define pal_lld_writegroup(port, mask, offset, bits) (void)bits
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/**
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* @brief Pads group mode setup.
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@@ -268,8 +276,8 @@ typedef uint8_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_setgroupmode(port, mask, offset, mode) \
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_pal_lld_setgroupmode(port, mask << offset, mode)
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#define pal_lld_setgroupmode(port, mask, offset, mode) \
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_pal_lld_setgroupmode(port, mask << offset, mode)
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/**
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* @brief Reads a logical state from an I/O pad.
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@@ -285,8 +293,8 @@ typedef uint8_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_readpad(port, pad) \
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(LPC_GPIO->B[((port) * 32) + (pad)])
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#define pal_lld_readpad(port, pad) \
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(LPC_GPIO->B[((port) * 32) + (pad)])
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/**
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* @brief Writes a logical state on an output pad.
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@@ -303,8 +311,8 @@ typedef uint8_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_writepad(port, pad, bit) \
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((LPC_GPIO->B[((port) * 32) + (pad)]) = (bit))
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#define pal_lld_writepad(port, pad, bit) \
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((LPC_GPIO->B[((port) * 32) + (pad)]) = (bit))
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/**
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* @brief Sets a pad logical state to @p PAL_HIGH.
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@@ -317,8 +325,8 @@ typedef uint8_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_setpad(port, pad) \
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(LPC_GPIO->SET[(port)] = 1 << (pad))
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#define pal_lld_setpad(port, pad) \
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(LPC_GPIO->SET[(port)] = 1 << (pad))
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/**
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* @brief Clears a pad logical state to @p PAL_LOW.
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@@ -331,7 +339,7 @@ typedef uint8_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_clearpad(port, pad) \
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#define pal_lld_clearpad(port, pad) \
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(LPC_GPIO->CLR[(port)] = 1 << (pad))
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/**
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@@ -345,8 +353,8 @@ typedef uint8_t iopadid_t;
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*
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* @notapi
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*/
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#define pal_lld_togglepad(port, pad) \
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(LPC_GPIO->NOT[(port)] = 1 << (pad))
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#define pal_lld_togglepad(port, pad) \
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(LPC_GPIO->NOT[(port)] = 1 << (pad))
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/**
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* @brief Pad mode setup.
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@@ -362,7 +370,7 @@ typedef uint8_t iopadid_t;
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*
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* @notapi
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*/
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//#define pal_lld_setpadmode(port, pad, mode)
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// #define pal_lld_setpadmode(port, pad, mode)
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#if !defined(__DOXYGEN__)
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extern const PALConfig pal_default_config;
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@@ -371,10 +379,10 @@ extern const PALConfig pal_default_config;
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#ifdef __cplusplus
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extern "C" {
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#endif
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void _pal_lld_init(const PALConfig *config);
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode);
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void _pal_lld_init(const PALConfig* config);
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode);
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#ifdef __cplusplus
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}
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#endif
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