PRALINE Tx and clock fix (Pr 3192 takeover (#3198) )

* fix clock init and add mayhem tx capacity
* aligned external clock and RX config
* fix(clock): cap TX interpolation to x16 to prevent doubled waveform speed

  The TX gateware only implements interpolation factors x1..x16 (tx_intrp
  0..4), but the rate search could select n==5 (x32) for very low TX
  sample rates. That left the AFE/CLK0/CLK1 running at the x32 rate while
  the FPGA only interpolated by x16, clocking the TX datapath at twice the
  gateware output rate. Cap afe_rate and _resampling_n to the x16 limit in
  TX so the clocks stay aligned with the interpolation setting.

* fix(praline): source PLL1 from 40MHz GP_CLKIN instead of 12MHz XTAL

  For the intermediate 90-110MHz PLL1 stepping stage, source PLL1 from
  GP_CLKIN (Si5351 CLK2/MCU_CLK at 40MHz) giving N=2, M=10, Fclk=100MHz,
  rather than the on-chip 12MHz XTAL bootstrap path. This matches the
  non-PRALINE path. Remove the dead commented-out XTAL enable/PLL code.

* docs(fpga_bridge): correct register 0x03 description for PRALINE gateware

  Register 0x03 is RX_DIGITAL_GAIN in RX and TX_NCO_CTRL in TX, not
  RX_PSTEP.

* Fix fpga_tx_set_nco_enable to use FPGA_REG3_TX_NCO_CTRL (0x03)

firmware/common/hackrf_hal.hpp

@@ -54,6 +54,12 @@ constexpr ClockFrequency max283x_reference_f = 40000000U;
 constexpr ClockFrequency mcu_clkin_og_f = 40000000U;
 constexpr ClockFrequency mcu_clkin_r9_f = 10000000U;
 
+#ifdef PRALINE
+constexpr int8_t default_tx_gain_db = 16;
+#else
+constexpr int8_t default_tx_gain_db = 35;
+#endif
+
 constexpr uint8_t si5351_i2c_address = 0x60;
 
 /* Clock Generator */