portapack-mayhem/mayhem-firmware
1
0
Fork 0
mirror of https://github.com/portapack-mayhem/mayhem-firmware.git synced 2026-09-01 12:29:04 +00:00
Code Issues Packages Projects Releases 10 Wiki Activity

PRALINE Tx and clock fix (Pr 3192 takeover (#3198) )

Browse Source 
* fix clock init and add mayhem tx capacity
* aligned external clock and RX config
* fix(clock): cap TX interpolation to x16 to prevent doubled waveform speed

  The TX gateware only implements interpolation factors x1..x16 (tx_intrp
  0..4), but the rate search could select n==5 (x32) for very low TX
  sample rates. That left the AFE/CLK0/CLK1 running at the x32 rate while
  the FPGA only interpolated by x16, clocking the TX datapath at twice the
  gateware output rate. Cap afe_rate and _resampling_n to the x16 limit in
  TX so the clocks stay aligned with the interpolation setting.

* fix(praline): source PLL1 from 40MHz GP_CLKIN instead of 12MHz XTAL

  For the intermediate 90-110MHz PLL1 stepping stage, source PLL1 from
  GP_CLKIN (Si5351 CLK2/MCU_CLK at 40MHz) giving N=2, M=10, Fclk=100MHz,
  rather than the on-chip 12MHz XTAL bootstrap path. This matches the
  non-PRALINE path. Remove the dead commented-out XTAL enable/PLL code.

* docs(fpga_bridge): correct register 0x03 description for PRALINE gateware

  Register 0x03 is RX_DIGITAL_GAIN in RX and TX_NCO_CTRL in TX, not
  RX_PSTEP.

* Fix fpga_tx_set_nco_enable to use FPGA_REG3_TX_NCO_CTRL (0x03)
This commit is contained in:
gullradriel
2026-05-31 12:44:40 +02:00
committed by GitHub
parent 4e56d0f420
commit 8f5b25b10d
11 changed files with 241 additions and 201 deletions
Download Patch File Download Diff File Expand all files Collapse all files
firmware/application/portapack.cpp
+11 -16
View File
@@ -360,19 +360,12 @@ static void set_cpu_clock_speed() {
/* Step into the 90-110MHz M4 clock range */
#ifdef PRALINE
/* PRALINE: Enable and use 12MHz XTAL directly (no GP_CLKIN from Si5351) */
/* Step 1: Enable the crystal oscillator */
LPC_CGU->XTAL_OSC_CTRL.ENABLE = 0; // 0 = enable (active low)
LPC_CGU->XTAL_OSC_CTRL.HF = 0; // 0 = low frequency mode (1-20MHz)
/* Step 2: Wait for oscillator to stabilize (~250us at IRC speed) */
volatile uint32_t delay = 3000; // ~250us at 12MHz IRC
while (delay--);
/* Step 3: Configure PLL1 from XTAL
* Fclkin = 12M, /N=1 = 12M, Fcco = 12M * 17 = 204M
* Fclk = Fcco / (2*(P=1)) = 102M
/* PRALINE: source PLL1 from GP_CLKIN, which is driven by the Si5351
* CLK2/MCU_CLK output at 40MHz (see ClockManager Si5351 setup). The
* on-chip 12MHz XTAL bootstrap path is intentionally not used here.
*
* Fclkin = 40M (GP_CLKIN), /N=2 = 20M, Fcco = 20M * 10 = 200M
* Fclk = Fcco / (2*(P=1)) = 100M
*/
cgu::pll1::ctrl({
.pd = 1,
@@ -381,10 +374,11 @@ static void set_cpu_clock_speed() {
.direct = 0,
.psel = 0,
.autoblock = 1,
.nsel = 0, // N = 1
.msel = 16, // M = 17, so 12MHz * 17 = 204MHz
.clk_sel = cgu::CLK_SEL::XTAL,
.nsel = 1UL, // N = 2
.msel = 9UL, // M = 10
.clk_sel = cgu::CLK_SEL::GP_CLKIN,
});
#else
/* OG:
* Fclkin = 40M, /N=2 = 20M, Fcco = 20M * 10 = 200M
@@ -613,6 +607,7 @@ init_status_t init() {
cgu::pll1::disable();
set_cpu_clock_speed();
/* sample max: 1023 sample_t AKA uint16_t
* touch_sensitivity: range: 1 to 128
* threshold range: 1023/1 to 1023/128 = 1023 to 8