praline without the much fixed ram (#3123)

firmware/application/portapack.cpp

@@ -636,7 +636,7 @@ init_status_t init() {
     // This function returns LD_SUCCESS (0) if the FPGA confirms the bitstream
     // Call fpga_bridge_init and continue boot regardless of result
     // (Watchdog was resetting device when we halted with while(1))
-    int load_result = fpga_bridge_init();
+    int load_result = fpga_bridge_init(&shared_memory.bb_data.data[0]);
     (void)load_result;  // Ignore result for now, just let boot continue
 
     /* RELEASE FPGA RESET */

firmware/chibios-portapack/boards/PORTAPACK_APPLICATION/fpga_bridge.c

@@ -135,7 +135,6 @@
 #define FPGA_TX_DEFAULT_INTERP 0x00     /* No interpolation */
 #define FPGA_TX_DEFAULT_PHASE_STEP 0x00 /* Zero phase step */
 
-
 // ============================================================================
 // Static Variables - Declare BEFORE use
 // ============================================================================
@@ -148,7 +147,7 @@
     const uint8_t* mem_ptr;  // Current read position in SPIFI memory
     size_t next_block_sz;
     uint8_t init_flag;
-      uint8_t buffer[4096 + 2];  // Compressed block + next size
+    uint8_t buffer[4128 + 2];  // Compressed block + next size
 };
 
 // ============================================================================
@@ -171,12 +170,15 @@
 // SSP1 transfer one byte
 static uint8_t ssp1_transfer_byte(uint8_t data) {
     // Wait for TX FIFO not full
-      while ((SSP1_SR_LOCAL & SSP_SR_TNF_LOCAL) == 0) {}
+    while ((SSP1_SR_LOCAL & SSP_SR_TNF_LOCAL) == 0) {
+    }
     SSP1_DR_LOCAL = data;
     // Wait for not busy
-      while (SSP1_SR_LOCAL & SSP_SR_BSY_LOCAL) {}
+    while (SSP1_SR_LOCAL & SSP_SR_BSY_LOCAL) {
+    }
     // Wait for RX FIFO not empty
-      while ((SSP1_SR_LOCAL & SSP_SR_RNE_LOCAL) == 0) {}
+    while ((SSP1_SR_LOCAL & SSP_SR_RNE_LOCAL) == 0) {
+    }
     return SSP1_DR_LOCAL;
 }
 
@@ -258,7 +260,6 @@
 //   Read:  Send [reg & 0x7F, 0x00, 0x00] -> value in byte 3
 //   Write: Send [(reg | 0x80), value, 0x00]
 
-
 // ============================================================================
 // SPI Mode Switching
 // ============================================================================
@@ -283,7 +284,6 @@
     SSP1_CR1_LOCAL = SSP_CR1_SSE;  // Enable SSP1
 }
 
-
 // ============================================================================
 // Low-Level SPI Register Access (internal, no mode switch)
 // ============================================================================
@@ -448,7 +448,6 @@
 // This is equivalent to fpga_init() in the reference HackRF firmware
 /* fpga_register_init with consistent values */
 static void fpga_register_init(void) {
-
     /* Boot into RX mode */
     current_mode = FPGA_MODE_RX;
 
@@ -485,6 +484,10 @@
 
     // Finish at end marker (block_sz == 0)
     if (block_sz == 0) return 0;
+    if (block_sz > 4128) {
+        // Flash corruption detected! Return 0 to abort programming safely.
+        return 0;
+    }
 
     // Read compressed block from SPIFI memory
     memcpy(ctx->buffer, ctx->mem_ptr, block_sz + 2);
@@ -499,7 +502,7 @@
 
 // Program iCE40 FPGA using SPIFI memory-mapped data
 // Based on ice40_spi_syscfg_program() from ice40_spi.c
-  static bool program_fpga_from_spifi(const uint8_t* bitstream_start) {
+static bool program_fpga_from_spifi(const uint8_t* bitstream_start, uint8_t* mem_base) {
     // Drive CRESET_B = 0, SPI_SS = 0
     fpga_creset_low();
     fpga_cs_low();
@@ -518,17 +521,19 @@
     ssp1_transfer_byte(0);
 
     // Send configuration image
-      // Use static buffers to avoid stack overflow (~8KB would be needed)
-      static uint8_t out_buffer[4096];
-      static struct spifi_fpga_read_ctx ctx;
-      ctx.mem_ptr = bitstream_start;
-      ctx.next_block_sz = 0;
-      ctx.init_flag = 0;
+    // Use  buffers to avoid stack overflow (~8KB would be needed)
+    uint8_t* out_buffer = mem_base;
+    struct spifi_fpga_read_ctx* ctx = (struct spifi_fpga_read_ctx*)(out_buffer + 4096);
+    memset(ctx, 0, sizeof(struct spifi_fpga_read_ctx));
+    memset(out_buffer, 0, 4096);
+    ctx->mem_ptr = bitstream_start;
+    ctx->next_block_sz = 0;
+    ctx->init_flag = 0;
 
     fpga_cs_low();
     // Full LZ4 decompress and send all bytes
     for (;;) {
-          size_t read_sz = spifi_fpga_read_block_cb(&ctx, out_buffer);
+        size_t read_sz = spifi_fpga_read_block_cb(ctx, out_buffer);
         if (read_sz == 0) break;
         for (size_t j = 0; j < read_sz; j++) {
             ssp1_transfer_byte(out_buffer[j]);
@@ -567,7 +572,7 @@
 // Main Initialization Entry Point
 // ============================================================================
 
-  int fpga_bridge_init(void) {
+int fpga_bridge_init(uint8_t* mem_base) {
     // Enable SSP1 clock for FPGA programming
     // Use PLL1 (204MHz) to match original HackRF - IRC (12MHz) is 17x too slow
     CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_AUTOBLOCK(1) |
@@ -601,7 +606,7 @@
     const uint8_t* bitstream_start = (const uint8_t*)(FPGA_BITSTREAM_MEM_ADDR + bitstream_offset);
 
     // Full FPGA programming
-      bool success = program_fpga_from_spifi(bitstream_start);
+    bool success = program_fpga_from_spifi(bitstream_start, mem_base);
 
     // Initialize FPGA registers immediately after programming
     if (success) {
@@ -614,7 +619,6 @@
         // Now switch to MAX2831 mode
         ssp1_set_mode_max2831();
     }
-
     return success ? 0 : 2;
 }
 #else

firmware/chibios-portapack/boards/PORTAPACK_APPLICATION/fpga_bridge.h

@@ -102,7 +102,7 @@ typedef enum {
 
 /* Initialize the FPGA - loads bitstream from SPIFI flash
  * Returns: 0 on success, non-zero on failure */
-int fpga_bridge_init(void);
+int fpga_bridge_init(uint8_t* mem_base);
 
 /* Set operating mode - MUST be called before using mode-specific functions
  * This ensures registers 3-5 are interpreted correctly */