mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-08-20 14:39:01 +00:00
add external clock detect method (#3180)
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@@ -424,17 +424,34 @@ using namespace hackrf::one;
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void ClockManager::init_clock_generator() {
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void ClockManager::init_clock_generator() {
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#ifdef PRALINE
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#ifdef PRALINE
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// PRALINE: Configure clock input mux GPIO
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// thoese PIN can review platform_scu file
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// GPIO0_15 (clkin_ctrl) selects GP_CLKIN source:
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// have many conflict and modify for clock init
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// 0 = P1 connector (external)
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// P2_10 -> GPIO0[14] P1_CTRL0
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// 1 = P22 (internal Si5351 CLK2)
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LPC_SCU->SFSP[2][10] = 0xF0;
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constexpr GPIO gpio_clkin_ctrl = gpio[GPIO0_15];
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// P6_8 -> GPIO5[16] P1_CTRL1
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gpio_clkin_ctrl.output();
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LPC_SCU->SFSP[6][8] = 0xF4;
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gpio_clkin_ctrl.write(1); // CLKIN_SIGNAL_P22 = 1 = internal Si5351 CLK2
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// P6_9 -> GPIO3[5] P1_CTRL2
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LPC_SCU->SFSP[6][9] = 0xF0;
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// P1_20 -> GPIO0[15] CLKIN_CTRL
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LPC_SCU->SFSP[1][20] = 0xF0;
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constexpr GPIO gpio_p1_ctrl0 = gpio[GPIO0_14];
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constexpr GPIO gpio_p1_ctrl1 = gpio[GPIO5_16];
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constexpr GPIO gpio_p1_ctrl2 = gpio[GPIO3_5];
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constexpr GPIO gpio_clkin_ctrl = gpio[GPIO0_15];
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gpio_p1_ctrl0.output();
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gpio_p1_ctrl1.output();
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gpio_p1_ctrl2.output();
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gpio_clkin_ctrl.output();
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// P1 control = 100 and choose P22 clock external clock on portapack
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gpio_p1_ctrl0.write(0);
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gpio_p1_ctrl1.write(0);
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gpio_p1_ctrl2.write(1);
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gpio_clkin_ctrl.write(1);
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chThdSleepMilliseconds(20);
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// Also enable MCU clock gate (GPIO0_8)
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gpio_r9_mcu_clk_en.output();
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gpio_r9_mcu_clk_en.write(1);
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#else
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#else
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// HackRF One r9: GPIO0_8 (mcu_clk_en) gates Si5351 CLK2/CLK7 to GP_CLKIN
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// HackRF One r9: GPIO0_8 (mcu_clk_en) gates Si5351 CLK2/CLK7 to GP_CLKIN
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if (hackrf_r9) {
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if (hackrf_r9) {
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@@ -458,10 +475,23 @@ void ClockManager::init_clock_generator() {
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* 4. Reset PLLs
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* 4. Reset PLLs
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* 5. Enable outputs
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* 5. Enable outputs
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*/
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*/
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clock_generator.set_pll_input_sources(si5351a_pll_input_sources);
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// change there detect method same as hackrf one
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// PLLA -> XTAL,PLLB -> CLKIN
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/* Skip MCU CLKIN setup and reference detection for PRALINE - not applicable */
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clock_generator.set_pll_input_sources(si5351c_pll_input_sources);
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reference = Reference{ReferenceSource::Xtal, 0}; // PLLA
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// although the name a and the branch define CLK2 MCU CLOCK
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// only use CLK2
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auto si5351_clock_control_common = si5351a_clock_control_common;
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constexpr size_t clock_generator_output_pro_mcu_clkin = 2;
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// clk_src define CLKIN
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clock_generator.set_clock_control(
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clock_generator_output_pro_mcu_clkin,
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si5351_clock_control_common[clock_generator_output_pro_mcu_clkin]
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.clk_src(ClockControl::ClockSource::CLKIN)
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.clk_pdn(ClockControl::ClockPowerDown::Power_On));
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clock_generator.enable_output(clock_generator_output_pro_mcu_clkin);
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chThdSleepMilliseconds(20);
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// should be extern icon and 10MHz
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reference = choose_reference();
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/* Clock control will be set AFTER multisynth configuration - see below */
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/* Clock control will be set AFTER multisynth configuration - see below */
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#else
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#else
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