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Updated praline low and high band tuning (#3030)

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* Updated harckrf_gpio methods to more closely reflect hackrf_usb. Added some ui debug updates to RFFC5072 Status View.

* Updated tuning tables for tuning.cpp. Remnoved 15MHz lower limit in max2831.cpp since lower bandwidths don't seem to be causing lower band issues. Added more opportunities for clocks to stabalize at startup in board.cpp. Added/amended UI to help with addresssing low band tuning issues. Cleaned up stale comments in radio.cpp.

* Ran format-code.sh

* Updated to remove commented lines as part of clean up addressing review comments.
This commit is contained in:
stafur
2026-02-22 19:40:49 -05:00
committed by GitHub
parent 1ad092f341
commit 85eaa9d800
10 changed files with 413 additions and 162 deletions
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firmware/chibios-portapack/boards/PORTAPACK_APPLICATION/board.cpp
+31 -15
View File
@@ -906,19 +906,19 @@ extern "C" void boardInit(void) {
LPC_SCU->SFSP[6][7] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
LPC_GPIO->DIR[5] |= (1 << 15);
LPC_GPIO->CLR[5] = (1 << 15); /* Clear = enable 3.3V aux */
{ volatile uint32_t delay = 100000; while(delay--); }
{ volatile uint32_t delay = 200000; while(delay--); }
/* Enable 1.2V for FPGA - P8_7 = GPIO4[7], active high */
LPC_SCU->SFSP[8][7] = 0x10;
LPC_GPIO->DIR[4] |= (1 << 7);
LPC_GPIO->SET[4] = (1 << 7);
{ volatile uint32_t delay = 100000; while(delay--); }
{ volatile uint32_t delay = 200000; while(delay--); }
/* Enable VAA for RF - P8_1 = GPIO4[1], active low */
LPC_SCU->SFSP[8][1] = 0x10;
LPC_GPIO->DIR[4] |= (1 << 1);
LPC_GPIO->CLR[4] = (1 << 1);
{ volatile uint32_t delay = 100000; while(delay--); }
{ volatile uint32_t delay = 200000; while(delay--); }
/* Configure RFFC5072 pins for PRALINE */
/* Set GPIO directions for RFFC5072 SPI pins */
@@ -937,6 +937,7 @@ extern "C" void boardInit(void) {
/* SCU configured in PAL array above with mode=4 */
LPC_GPIO->CLR[5] = (1 << 6); /* Default low (mixer enabled) */
LPC_GPIO->DIR[5] |= (1 << 6); /* Output */
{ volatile uint32_t delay = 200000; while(delay--); }
/* Configure Port D pins for PRALINE (use SFSPD registers) */
/* PD_14 = GPIO6[28] MAX2831 chip select */
@@ -953,6 +954,7 @@ extern "C" void boardInit(void) {
LPC_SCU->SFSPD[16] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
LPC_GPIO->SET[6] |= (1 << 30); /* CS high (inactive) */
LPC_GPIO->DIR[6] |= (1 << 30); /* Output */
{ volatile uint32_t delay = 200000; while(delay--); }
/* Configure Port E pins for MAX2831 control (use SFSPE registers) */
/* PE_1 = GPIO7[1] MAX2831 ENABLE */
@@ -963,6 +965,7 @@ extern "C" void boardInit(void) {
LPC_SCU->SFSPE[2] = 0xF4; /* SCU_GPIO_FAST | FUNCTION4 */
LPC_GPIO->CLR[7] = (1 << 2); /* Start in shutdown mode */
LPC_GPIO->DIR[7] |= (1 << 2); /* Output */
{ volatile uint32_t delay = 200000; while(delay--); }
/* Configure Port 6 pins for RF path control */
/* P6_3 = GPIO3[2] Mixer enable (inverted: 0 = mixer ON) */
@@ -973,6 +976,7 @@ extern "C" void boardInit(void) {
LPC_SCU->SFSP[6][5] = 0xF0; /* SCU_GPIO_FAST | FUNCTION0 */
LPC_GPIO->CLR[3] = (1 << 4); /* TX off by default (RX mode) */
LPC_GPIO->DIR[3] |= (1 << 4); /* Output */
{ volatile uint32_t delay = 200000; while(delay--); }
/* Configure Port A pins for RF path control */
/* PA_1 = GPIO4[8] LPF enable */
@@ -983,22 +987,30 @@ extern "C" void boardInit(void) {
LPC_SCU->SFSP[0xA][2] = 0xF0; /* SCU_GPIO_FAST | FUNCTION0 */
LPC_GPIO->CLR[4] = (1 << 9); /* RF amp off by default */
LPC_GPIO->DIR[4] |= (1 << 9); /* Output */
{ volatile uint32_t delay = 200000; while(delay--); }
/* Configure RFFC5072 control pins for PRALINE */
/* P5_4 = GPIO2[13] RFFC5072 ENX (active low: 0=enabled) */
LPC_SCU->SFSP[5][4] = 0xF0; /* FUNCTION0 (GPIO), no pulls */
/* P5_4 = GPIO2[13] RFFC5072 ENX - SPI chip select (managed by SPI driver) */
LPC_SCU->SFSP[5][4] = 0x10; /* FUNCTION0 (GPIO), pull-up, slow mode (matches HackRF USB) */
LPC_GPIO->DIR[2] |= (1 << 13); /* ENX: OUTPUT */
LPC_GPIO->CLR[2] = (1 << 13); /* ENX = 0 (ENABLED) */
/* P5_5 = GPIO2[14] RFFC5072 RESETX - FPGA controlled, MCU should not touch */
LPC_SCU->SFSP[5][5] = 0xF0; /* FUNCTION0 (GPIO), no pulls */
LPC_GPIO->DIR[2] &= ~(1 << 14); /* RESETX: INPUT (let FPGA control) */
LPC_GPIO->SET[2] = (1 << 13); /* ENX = 1 (deselected initially) */
{ volatile uint32_t delay = 200000; while(delay--); }
/* P5_5 = GPIO2[14] RFFC5072 RESETX (active high: 1=running) */
LPC_SCU->SFSP[5][5] = 0x10; /* FUNCTION0 (GPIO), pull-up, slow mode (matches HackRF USB) */
LPC_GPIO->DIR[2] |= (1 << 14); /* RESETX: OUTPUT */
LPC_GPIO->SET[2] = (1 << 14); /* RESETX = 1 (RUNNING) */
{ volatile uint32_t delay = 200000; while(delay--); }
/* Ensure RESETX is stable */
for (volatile int i = 0; i < 10; i++) {
LPC_GPIO->W2[14] = 1;
}
/* PD_11 = GPIO6[25] RFFC5072 Lock Detect (input) */
LPC_SCU->SFSP[0xD][11] = 0xF4; /* FUNCTION4 (GPIO), no pulls */
/* Small delay for signals to stabilize */
for (volatile int i = 0; i < 10000; i++) {}
LPC_SCU->SFSPD[11] = 0x10; /* FUNCTION0 (GPIO), pull-up (matches HackRF USB) */
LPC_GPIO->DIR[6] &= ~(1 << 25); /* LD: INPUT */
{ volatile uint32_t delay = 200000; while(delay--); }
/* Configure PRALINE-specific SGPIO pins for FPGA sample interface.
* These override the HackRF One pin config from pins_setup.
@@ -1018,6 +1030,7 @@ extern "C" void boardInit(void) {
LPC_SCU->SFSP[8][2] = 0xF4; /* SCU_GPIO_FAST | func 4 */
/* SGPIO11 = P1_17 function 6 (HOST_DIRECTION - output to FPGA, tells FPGA TX vs RX) */
LPC_SCU->SFSP[1][17] = 0xF6; /* SCU_GPIO_FAST | func 6 */
{ volatile uint32_t delay = 200000; while(delay--); }
/* SGPIO data pins (SGPIO0-7) - all 8 bits required for sample data */
LPC_SCU->SFSP[0][0] = 0xF3; /* SGPIO0: P0_0 function 3, HOST_DATA0 */
@@ -1028,6 +1041,7 @@ extern "C" void boardInit(void) {
LPC_SCU->SFSP[6][6] = 0xF2; /* SGPIO5: P6_6 function 2, HOST_DATA5 */
LPC_SCU->SFSP[2][2] = 0xF0; /* SGPIO6: P2_2 function 0, HOST_DATA6 */
LPC_SCU->SFSP[1][0] = 0xF6; /* SGPIO7: P1_0 function 6, HOST_DATA7 */
{ volatile uint32_t delay = 200000; while(delay--); }
// Trigger FPGA bitstream loading via fpga bridge
// Attempt to load the FPGA bitstream
@@ -1041,11 +1055,13 @@ extern "C" void boardInit(void) {
// Turn off all LEDs to start
// PRALINE LEDs are active-low: SET (HIGH) = OFF, CLR (LOW) = ON
LPC_GPIO->SET[2] = (1 << 1) | (1 << 2) | (1 << 8);
{ volatile uint32_t delay = 200000; while(delay--); }
// Call fpga_bridge_init and continue boot regardless of result
// (Watchdog was resetting device when we halted with while(1))
int load_result = fpga_bridge_init();
(void)load_result; // Ignore result for now, just let boot continue
{ volatile uint32_t delay = 200000; while(delay--); }
// Keep LEDs off after FPGA load
LPC_GPIO->SET[2] = (1 << 1) | (1 << 2) | (1 << 8);