portapack-mayhem/mayhem-firmware
1
0
Fork 0
mirror of https://github.com/portapack-mayhem/mayhem-firmware.git synced 2026-08-19 22:24:02 +00:00
Code Issues Packages Projects Releases 10 Wiki Activity

Updated praline low and high band tuning (#3030)

Browse Source 
* Updated harckrf_gpio methods to more closely reflect hackrf_usb. Added some ui debug updates to RFFC5072 Status View.

* Updated tuning tables for tuning.cpp. Remnoved 15MHz lower limit in max2831.cpp since lower bandwidths don't seem to be causing lower band issues. Added more opportunities for clocks to stabalize at startup in board.cpp. Added/amended UI to help with addresssing low band tuning issues. Cleaned up stale comments in radio.cpp.

* Ran format-code.sh

* Updated to remove commented lines as part of clean up addressing review comments.
This commit is contained in:
stafur
2026-02-22 19:40:49 -05:00
committed by GitHub
parent 1ad092f341
commit 85eaa9d800
10 changed files with 413 additions and 162 deletions
Download Patch File Download Diff File Expand all files Collapse all files
firmware/application/radio.cpp
+21 -12
View File
@@ -208,15 +208,18 @@ void set_direction(const rf::Direction new_direction) {
}
#ifdef PRALINE
// TEST: Force baseband invert for Praline (like r9)
// baseband_invert = (direction == rf::Direction::Receive);
// Praline: Control Q inversion via FPGA register
uint8_t ctrl_reg = 0x01; // DC_BLOCK enabled
if (mixer_invert ^ baseband_invert) {
ctrl_reg |= 0x02; // Set Q_INVERT bit
// CORRECT: FPGA register 1 only controls DC_BLOCK
fpga_debug_register_write(1, 0x01); // DC_BLOCK only, no QUARTER_SHIFT!
// Q inversion controlled by GPIO0[13] (SGPIO12), not FPGA register
bool q_invert = mixer_invert ^ baseband_invert;
if (q_invert) {
LPC_GPIO->SET[0] = (1 << 13); // SGPIO12 = 1 (Q inverted)
} else {
LPC_GPIO->CLR[0] = (1 << 13); // SGPIO12 = 0 (Q normal)
}
fpga_debug_register_write(1, ctrl_reg);
ssp1_arbiter.invalidate();
#else
baseband_cpld.set_invert(mixer_invert ^ baseband_invert);
@@ -282,13 +285,19 @@ bool set_tuning_frequency(const rf::Frequency frequency) {
// TEST: Force baseband invert for Praline (like r9)
// baseband_invert = (direction == rf::Direction::Receive);
// PRALINE: Update FPGA Q inversion when tuning changes
uint8_t ctrl_reg = 0x01; // DC_BLOCK enabled
if (mixer_invert ^ baseband_invert) {
ctrl_reg |= 0x02; // Set Q_INVERT bit
// CORRECT: FPGA register 1 only controls DC_BLOCK
fpga_debug_register_write(1, 0x01); // DC_BLOCK only, no QUARTER_SHIFT!
// Q inversion controlled by GPIO0[13] (SGPIO12), not FPGA register
bool q_invert = mixer_invert ^ baseband_invert;
if (q_invert) {
LPC_GPIO->SET[0] = (1 << 13); // SGPIO12 = 1 (Q inverted)
} else {
LPC_GPIO->CLR[0] = (1 << 13); // SGPIO12 = 0 (Q normal)
}
fpga_debug_register_write(1, ctrl_reg);
ssp1_arbiter.invalidate();
// Log this value somewhere you can see it
uint32_t written_r15 = first_if.read(15);
#else