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Gpio modify v4 (#3266)

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* Refactor GPIO handling for RFFC5072: update pin mappings and simplify initialization

* Refactor GPIO handling: replace portapack::gpio_dfu with dfu_button and clean up unused GPIOs

* Refactor MAX283x GPIO handling: update pin mappings and simplify initialization

* Refactor GPIO handling: update MAX2831 shutdown pin configuration

* Refactor GPIO handling: add MAX2831 RXHP and RXTX control, update related configurations

* Refactor MAX2831 frequency setting to include reference divider parameter and improve validation checks

* Refactor MAX2831 frequency setting to remove reference divider parameter and improve frequency validation

* copilot
This commit is contained in:
Pezsma
2026-07-10 21:37:41 +02:00
committed by GitHub
parent 87eb8e5863
commit 8561ff32b3
14 changed files with 325 additions and 286 deletions
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firmware/application/config_mode.cpp
+4 -5
View File
@@ -61,7 +61,6 @@ uint32_t blink_patterns[] = {
void config_mode_run() {
configure_pins_portapack();
portapack::gpio_dfu.input();
portapack::persistent_memory::cache::init();
if (hackrf_r9) {
@@ -80,14 +79,14 @@ void config_mode_run() {
config_mode_blink_until_dfu();
}
auto last_dfu_btn = portapack::gpio_dfu.read();
auto last_dfu_btn = dfu_button.read();
int32_t counter = 0;
int8_t blink_pattern_value = portapack::persistent_memory::config_cpld() +
(portapack::persistent_memory::config_disable_external_tcxo() ? 5 : 0);
while (true) {
auto dfu_btn = portapack::gpio_dfu.read();
auto dfu_btn = dfu_button.read();
auto dfu_clicked = last_dfu_btn == true && dfu_btn == false;
last_dfu_btn = dfu_btn;
@@ -137,7 +136,7 @@ void config_mode_blink_until_dfu() {
led_usb.setInactive();
chThdSleepMilliseconds(115);
auto dfu_btn = portapack::gpio_dfu.read();
auto dfu_btn = dfu_button.read();
if (dfu_btn)
break;
}
@@ -145,7 +144,7 @@ void config_mode_blink_until_dfu() {
while (true) {
chThdSleepMilliseconds(10);
auto dfu_btn = portapack::gpio_dfu.read();
auto dfu_btn = dfu_button.read();
if (!dfu_btn)
break;
}
firmware/application/hw/max2831.cpp
+83 -20
View File
@@ -28,10 +28,15 @@
#include "max2831.hpp"
#include "portapack_adc.hpp"
#include "hackrf_hal.hpp"
#include "hackrf_gpio.hpp"
using namespace hackrf::one;
#include "gpio.hpp"
using namespace gpio_control;
#include "ch.h"
#include "hal.h"
@@ -151,7 +156,7 @@ void MAX2831::set_mode(const Mode mode) {
* RX: ENABLE=1, RXTX=0
* TX: ENABLE=1, RXTX=1
*
* Note: gpio_max2831_rx_enable is the RXTX mode select pin.
* Note: max2831_rxtx_enable is the RXTX mode select pin.
* RXTX=0 selects RX, RXTX=1 selects TX.
*/
@@ -174,26 +179,26 @@ void MAX2831::set_mode(const Mode mode) {
switch (mode) {
default:
case Mode::Shutdown:
gpio_max2831_rx_enable.write(0); /* RXTX=0 */
gpio_max283x_enable.write(0); /* ENABLE=0 */
max2831_rxtx_enable.setInactive(); /* RXTX=0 */
max283x_enable.setInactive(); /* ENABLE=0 */
set_rssi_mux(0);
break;
case Mode::Standby:
gpio_max2831_rx_enable.write(1); /* RXTX=1 */
gpio_max283x_enable.write(0); /* ENABLE=0 */
max2831_rxtx_enable.setActive(); /* RXTX=1 */
max283x_enable.setInactive(); /* ENABLE=0 */
set_rssi_mux(0);
break;
case Mode::Transmit:
case Mode::Tx_Calibration:
gpio_max2831_rx_enable.write(1); /* RXTX=1 for TX */
gpio_max283x_enable.write(1); /* ENABLE=1 */
max2831_rxtx_enable.setActive(); /* RXTX=1 for TX */
max283x_enable.setActive(); /* ENABLE=1 */
set_rssi_mux(2); // transmit power
break;
case Mode::Receive:
case Mode::Rx_Calibration:
gpio_max2831_rx_enable.write(0); /* RXTX=0 for RX */
gpio_max283x_enable.write(1); /* ENABLE=1 */
set_rssi_mux(1); // RSSI
max2831_rxtx_enable.setInactive(); /* RXTX=0 for RX */
max283x_enable.setActive(); /* ENABLE=1 */
set_rssi_mux(1); // RSSI
break;
}
@@ -227,8 +232,15 @@ void MAX2831::set_lna_gain(const int_fast8_t db) {
} else {
gain_val = REG11_LNA_GAIN_M33;
}
max2831_rxhp.setActive(); // Fast DC offset compensation
set_reg_field(11, REG11_LNA_GAIN_MASK, gain_val);
flush_reg(11);
chThdSleepMicroseconds(2);
max2831_rxhp.setInactive();
}
void MAX2831::set_vga_gain(const int_fast8_t db) {
@@ -237,10 +249,18 @@ void MAX2831::set_vga_gain(const int_fast8_t db) {
if ((db & 0x1) || db > 62) {
return; /* Invalid: must be even and <= 62 */
}
int_fast8_t db_clipped = std::max(0, std::min(62, (int)db));
uint16_t value = (db_clipped >> 1) & 0x1f;
max2831_rxhp.setActive(); // Fast DC offset compensation
set_reg_field(11, REG11_RXVGA_GAIN_MASK, value);
flush_reg(11);
chThdSleepMicroseconds(2);
max2831_rxhp.setInactive();
}
/*
@@ -365,9 +385,9 @@ void MAX2831::set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum) {
void MAX2831::set_lpf_rf_bandwidth_tx(const uint32_t bandwidth_minimum) {
_desired_lpf_bw = bandwidth_minimum;
#ifdef PRALINE
gpio_control::aa_en.clear(); // Disable external AA filter for wideband operations
#endif
gpio_control::aa_en.setInactive(); // Disable external AA filter for wideband operations
if (_mode == Mode::Transmit || _mode == Mode::Tx_Calibration) {
set_lpf_bandwidth_internal(bandwidth_minimum);
}
@@ -461,13 +481,56 @@ void MAX2831::set_rx_buff_vcm(const size_t v) {
}
int8_t MAX2831::temp_sense() {
/* MAX2831 temperature sensor can be read via RSSI MUX.
* This would require:
* 1. Switch RSSI_MUX to temperature mode
* 2. Read the ADC
* 3. Switch back to RSSI mode
* For now, return a placeholder value. */
return 25; /* Room temperature placeholder */
bool not_in_rx = (_mode != Mode::Receive && _mode != Mode::Rx_Calibration);
if (not_in_rx) {
max2831_rxtx_enable.setInactive();
max283x_enable.setActive();
chThdSleepMilliseconds(1);
}
set_rssi_mux(3);
chThdSleepMilliseconds(5);
uint32_t saved_cr = LPC_ADC1->CR;
uint32_t cr_temp = saved_cr;
cr_temp &= ~0xFF;
cr_temp |= (1 << portapack::adc1_rssi_input);
if (((cr_temp >> 8) & 0xFF) == 0) {
cr_temp |= (0xFF << 8);
}
cr_temp &= ~(1 << 16);
cr_temp |= (1 << 21);
cr_temp &= ~(7 << 24);
cr_temp |= (1 << 24);
LPC_ADC1->CR = cr_temp;
uint32_t val;
while (((val = LPC_ADC1->DR[portapack::adc1_rssi_input]) & (1UL << 31)) == 0) {
__asm__("nop");
}
uint32_t adc_raw = (val >> 6) & 0x3FF;
LPC_ADC1->CR = saved_cr;
if (not_in_rx) {
set_mode(_mode);
} else {
set_rssi_mux(1);
}
float v_adc = (adc_raw / 1023.0f) * 3.3f;
constexpr float V_25_CELSIUS = 1.185f;
constexpr float SLOPE = 0.003f;
float temp = 25.0f + ((v_adc - V_25_CELSIUS) / SLOPE);
return static_cast<int8_t>(std::max(-128.0f, std::min(127.0f, temp)));
}
reg_t MAX2831::read(const address_t reg_num) {
firmware/application/hw/max2837.cpp
+8 -19
View File
@@ -19,12 +19,17 @@
* Boston, MA 02110-1301, USA.
*/
#ifndef PRALINE // not praline
#include "max2837.hpp"
#include "hackrf_hal.hpp"
#include "hackrf_gpio.hpp"
using namespace hackrf::one;
#include "gpio.hpp"
using namespace gpio_control;
#include "ch.h"
#include "hal.h"
@@ -99,12 +104,6 @@ constexpr uint32_t pll_factor = 1.0 / (4.0 / 3.0 / reference_frequency) + 0.5;
void MAX2837::init() {
set_mode(Mode::Shutdown);
#ifndef PRALINE
gpio_max283x_enable.output();
gpio_max2837_rxenable.output();
gpio_max2837_txenable.output();
#endif
_map.r.tx_gain.TXVGA_GAIN_SPI_EN = 1;
_map.r.tx_gain.TXVGA_GAIN_MSB_SPI_EN = 1;
_map.r.tx_gain.TXVGA_GAIN_SPI = 0x00;
@@ -159,12 +158,6 @@ void MAX2837::set_tx_LO_iq_phase_calibration(const size_t v) {
// TX calibration , Logic pins , ENABLE, RXENABLE, TXENABLE = 1,0,1 (5dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
set_mode(Mode::Tx_Calibration); // write to ram 3 LOGIC Pins .
#ifndef PRALINE
gpio_max283x_enable.output();
gpio_max2837_rxenable.output();
gpio_max2837_txenable.output();
#endif
_map.r.spi_en.CAL_SPI = 1; // Register Settings reg address 16, D1 (CAL mode 1)
_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (CHIP ENABLE 1)
flush_one(Register::SPI_EN);
@@ -214,7 +207,7 @@ void MAX2837::set_mode(const Mode mode) { // We set up the 3 Logic Pins ENABLE,
_mode = mode;
Mask mask = mode_mask(mode);
gpio_max283x_enable.write(toUType(mask) & toUType(Mask::Enable));
max283x_enable.write(toUType(mask) & toUType(Mask::Enable));
gpio_max2837_rxenable.write(toUType(mask) & toUType(Mask::RxEnable));
gpio_max2837_txenable.write(toUType(mask) & toUType(Mask::TxEnable));
}
@@ -352,12 +345,6 @@ void MAX2837::set_rx_LO_iq_phase_calibration(const size_t v) {
// RX calibration , Logic pins , ENABLE, RXENABLE, TXENABLE = 1,1,0 (3dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
set_mode(Mode::Rx_Calibration); // write to ram 3 LOGIC Pins .
#ifndef PRALINE
gpio_max283x_enable.output();
gpio_max2837_rxenable.output();
gpio_max2837_txenable.output();
#endif
_map.r.spi_en.CAL_SPI = 1; // Register Settings reg address 16, D1 (CAL mode 1)
_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (CHIP ENABLE 1)
flush_one(Register::SPI_EN);
@@ -419,3 +406,5 @@ int8_t MAX2837::temp_sense() {
}
} // namespace max2837
#endif // not PRALINE
firmware/application/hw/max2839.cpp
+6 -16
View File
@@ -19,6 +19,7 @@
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#ifndef PRALINE // not praline
#include "max2839.hpp"
@@ -26,6 +27,9 @@
#include "hackrf_gpio.hpp"
using namespace hackrf::one;
#include "gpio.hpp"
using namespace gpio_control;
#include "ch.h"
#include "hal.h"
@@ -100,11 +104,6 @@ static int_fast8_t requested_rx_vga_gain = 0;
void MAX2839::init() {
set_mode(Mode::Shutdown);
#ifndef PRALINE
gpio_max283x_enable.output();
gpio_max2839_rxtx.output();
#endif
_map.r.rxrf_1.MIMOmode = 1; /* enable RXINB */
_map.r.pa_drv.TXVGA_GAIN_SPI_EN = 1;
@@ -154,11 +153,6 @@ void MAX2839::set_tx_LO_iq_phase_calibration(const size_t v) {
// TX calibration , 2 x Logic pins , ENABLE, RXENABLE = 1,0, (2dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
set_mode(Mode::Tx_Calibration); // write to ram 3 LOGIC Pins .
#ifndef PRALINE
gpio_max283x_enable.output(); // max2839 has only 2 x pins + regs to decide mode.
gpio_max2839_rxtx.output(); // Here is combined rx & tx pin in one port.
#endif
_map.r.spi_en.CAL_SPI = 1; // Register Settings reg address 16, D1 (CAL mode 1)
_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (CHIP ENABLE 1)
flush_one(Register::SPI_EN);
@@ -207,7 +201,7 @@ void MAX2839::set_mode(const Mode mode) {
_mode = mode;
Mask mask = mode_mask(mode);
gpio_max283x_enable.write(toUType(mask) & toUType(Mask::Enable));
max283x_enable.write(toUType(mask) & toUType(Mask::Enable));
gpio_max2839_rxtx.write(toUType(mask) & toUType(Mask::RxTx));
}
@@ -395,11 +389,6 @@ void MAX2839::set_rx_LO_iq_phase_calibration(const size_t v) {
// RX calibration , Logic pins , ENABLE, RXENABLE, TXENABLE = 1,1,0 (3dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
set_mode(Mode::Rx_Calibration); // write to ram 3 LOGIC Pins .
#ifndef PRALINE
gpio_max283x_enable.output(); // max2839 has only 2 x pins + regs to decide mode.
gpio_max2839_rxtx.output(); // Here is combined rx & tx pin in one port.
#endif
_map.r.spi_en.CAL_SPI = 1; // Register Settings reg address 16, D1 (CAL mode 1)
_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (CHIP ENABLE 1)
flush_one(Register::SPI_EN);
@@ -447,3 +436,4 @@ int8_t MAX2839::temp_sense() {
}
} // namespace max2839
#endif // not PRALINE
firmware/application/hw/rffc507x.cpp
+9 -7
View File
@@ -26,9 +26,13 @@
#include "utility.hpp"
#include "hackrf_hal.hpp"
#include "hackrf_gpio.hpp"
using namespace hackrf::one;
#include "gpio.hpp"
using namespace gpio_control;
#include "hal.h"
#ifdef PRALINE
@@ -176,13 +180,11 @@ struct SynthConfig {
void RFFC507x::init() {
#ifdef PRALINE
gpio_control::rf5072_mix_en.setActive(); // RF5072_MIX_EN
rf5072_mix_en.setActive(); // RF5072_MIX_EN
#endif
gpio_rffc5072_resetx.set();
#ifndef PRALINE
gpio_rffc5072_resetx.output();
#endif
rffc5072_resetx.setInactive();
reset();
_bus.init();
@@ -195,9 +197,9 @@ void RFFC507x::reset() {
/* TODO: Is RESETB pin ignored if sdi_ctrl.sipin=1? Programming guide
* description of sdi_ctrl.sipin suggests the pin is not ignored.
*/
gpio_rffc5072_resetx.clear();
rffc5072_resetx.setActive();
halPolledDelay(ticks_during_reset);
gpio_rffc5072_resetx.set();
rffc5072_resetx.setInactive();
halPolledDelay(ticks_after_reset);
}
firmware/application/hw/rffc507x_spi.cpp
+13 -19
View File
@@ -23,50 +23,44 @@
#include "utility.hpp"
#include "hackrf_gpio.hpp"
using namespace hackrf::one;
#include "gpio.hpp"
using namespace gpio_control;
namespace rffc507x {
namespace spi {
void SPI::init() {
gpio_rffc5072_select.set();
gpio_rffc5072_clock.clear();
#ifndef PRALINE
gpio_rffc5072_select.output();
gpio_rffc5072_clock.output();
#endif
gpio_rffc5072_data.input();
gpio_rffc5072_data.clear();
rffc5072_select.setInactive();
rffc5072_clock.setInactive();
rffc5072_sdata.input();
rffc5072_sdata.setInactive();
}
inline void SPI::select(const bool active) {
gpio_rffc5072_select.write(!active);
rffc5072_select.setState(active);
}
inline void SPI::direction_out() {
gpio_rffc5072_data.output();
rffc5072_sdata.output();
}
inline void SPI::direction_in() {
gpio_rffc5072_data.input();
rffc5072_sdata.input();
}
inline void SPI::write_bit(const bit_t value) {
gpio_rffc5072_data.write(value);
rffc5072_sdata.write(value);
}
inline bit_t SPI::read_bit() {
return gpio_rffc5072_data.read() & 1;
return rffc5072_sdata.read() & 1;
}
inline bit_t SPI::transfer_bit(const bit_t bit_out) {
gpio_rffc5072_clock.clear();
rffc5072_clock.setInactive();
write_bit(bit_out);
const bit_t bit_in = read_bit();
gpio_rffc5072_clock.set();
rffc5072_clock.setActive();
return bit_in;
}
firmware/application/portapack.cpp
+1 -3
View File
@@ -57,13 +57,13 @@ using asahi_kasei::ak4951::AK4951;
#include "battery.hpp"
#include "gpio.hpp"
using namespace gpio_control;
extern "C" {
#include "platform_detect.h"
#ifdef PRALINE
#include "fpga_bridge.h"
#include "board.h"
#endif
}
@@ -74,11 +74,9 @@ const char* init_error = nullptr;
portapack::IO io{
portapack::gpio_dir,
portapack::gpio_lcd_rdx,
portapack::gpio_lcd_wrx,
portapack::gpio_io_stbx,
portapack::gpio_addr,
portapack::gpio_lcd_te,
portapack::gpio_dfu,
};
portapack::BacklightCAT4004 backlight_cat4004;
firmware/application/radio.cpp
+4 -4
View File
@@ -76,8 +76,8 @@ static constexpr uint32_t ssp_scr(
/* MAX2831 uses 9-bit SPI transfers */
static constexpr SPIConfig ssp_config_max283x = {
.end_cb = NULL,
.ssport = gpio_max283x_select.port(),
.sspad = gpio_max283x_select.pad(),
.ssport = map_max283x_select.gpio_port,
.sspad = map_max283x_select.gpio_pad,
.cr0 =
CR0_CLOCKRATE(ssp_scr(ssp1_pclk_f, ssp1_cpsr, max283x_spi_f) + 3) | CR0_FRFSPI | CR0_DSS9BIT,
.cpsr = ssp1_cpsr,
@@ -95,8 +95,8 @@ void set_rx_buff_vcm(const size_t v) {
/* MAX2837/MAX2839 use 16-bit SPI transfers */
static constexpr SPIConfig ssp_config_max283x = {
.end_cb = NULL,
.ssport = gpio_max283x_select.port(),
.sspad = gpio_max283x_select.pad(),
.ssport = map_max283x_select.gpio_port,
.sspad = map_max283x_select.gpio_pad,
.cr0 =
CR0_CLOCKRATE(ssp_scr(ssp1_pclk_f, ssp1_cpsr, max283x_spi_f) + 3) | CR0_FRFSPI | CR0_DSS16BIT,
.cpsr = ssp1_cpsr,
firmware/chibios-portapack/boards/PORTAPACK_APPLICATION/board.cpp
+133 -136
View File
@@ -60,8 +60,8 @@ const PALConfig pal_default_config = {
= boot_bit(p1_ctrl0, 0) // P2_10: P1_CTRL0, start low
| boot_bit(clkin_ctrl, 0) // P1_20: CLKIN_CTRL - start low
#else
= boot_bit(amp_bypass, 1) // P2_10: AMP_BYPASS
| (1 << 15) // P1_20: CS_XCVR
= boot_bit(amp_bypass, 1) // P2_10: AMP_BYPASS
| boot_bit(max283x_select, 1) // P1_20: !CS_XCVR
#endif
| boot_bit(dfu_boot_0, 0) // P1_1: 10K PU, BOOT0
| boot_bit(dfu_boot_1, 0) // P1_2: 10K PD, BOOT1
@@ -83,8 +83,8 @@ const PALConfig pal_default_config = {
= boot_bit(p1_ctrl0, 1) // P2_10: P1_CTRL0
| boot_bit(clkin_ctrl, 1) // P1_20: CLKIN_CTRL
#else
= boot_bit(amp_bypass, 1) // P2_10: AMP_BYPASS
| (1 << 15) // P1_20: CS_XCVR
= boot_bit(amp_bypass, 1) // P2_10: AMP_BYPASS
| boot_bit(max283x_select, 1) // P1_20: !CS_XCVR
#endif
| boot_bit(dfu_boot_0, 0) // P1_1: 10K PU, BOOT0
| boot_bit(dfu_boot_1, 0) // P1_2: 10K PD, BOOT1
@@ -153,10 +153,9 @@ const PALConfig pal_default_config = {
},
{
// GPIO2
.data = (1 << 14) // P5_5: MIXER_RESETX, 10K PU
.data = boot_bit(rffc5072_resetx, 1) // P5_5: !MIXER_RESETX
#ifdef PRALINE
| (0 << 15) // P5_6: unused on PRALINE
| (1 << 13) // P5_4: RFFC5072 ENX
| (0 << 12) // P5_3: unused on PRALINE
| (0 << 11) // P5_2: FPGA_CRESET
| (1 << 10) // P5_1: FPGA_SPI_CS
@@ -169,9 +168,7 @@ const PALConfig pal_default_config = {
| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
#else
| boot_bit(tx_amp, 0) // P5_6: TX_AMP
| (1 << 13) // P5_4: MIXER_ENX, 10K PU
| boot_bit(tx_amp, 0) // P5_6: TX_AMP
| boot_bit(rx_mix_bp, 1) // P5_3: RX_MIX_BP
| boot_bit(tx_mix_bp, 0) // P5_2: TX_MIX_BP
| boot_bit(lpf, 0) // P5_1: LPF
@@ -184,13 +181,13 @@ const PALConfig pal_default_config = {
| boot_bit(led_usb, 0) // P4_1: LED1 (USB)
#endif
| (1 << 7) // P5_7: CS_AD
| (0 << 5) // P4_5: RXENABLE
| boot_bit(rffc5072_select, 1) // P5_4: !MIXER_ENX
| (1 << 7) // P5_7: CS_AD
| (0 << 5) // P4_5: RXENABLE
,
.dir =
#ifdef PRALINE
(1 << 15) // P5_6: unused on PRALINE
| (1 << 13) // P5_4: RFFC5072 ENX
| (1 << 12) // P5_3: unused on PRALINE
| (1 << 11) // P5_2: FPGA_CRESET
| (1 << 10) // P5_1: FPGA_SPI_CS
@@ -200,22 +197,22 @@ const PALConfig pal_default_config = {
| (0 << 3) // P4_3: VBUSCTRL input
| (0 << 6) // P4_6: Input
#else
boot_bit(tx_amp, 1) // P5_6: TX_AMP
| (1 << 13) // P5_4: MIXER_ENX, 10K PU
| boot_bit(rx_mix_bp, 1) // P5_3: RX_MIX_BP
| boot_bit(tx_mix_bp, 1) // P5_2: TX_MIX_BP
| boot_bit(lpf, 1) // P5_1: LPF
| (0 << 9) // P5_0: Varies by revision
| boot_bit(hpf, 1) // P4_0: HPF
| boot_bit(sgpio_9, 0) // P4_3: SGPIO9, HOST_CAPTURE
| (1 << 6) // P4_6: XCVR_EN, 10K PD
boot_bit(tx_amp, 1) // P5_6: TX_AMP
| boot_bit(rx_mix_bp, 1) // P5_3: RX_MIX_BP
| boot_bit(tx_mix_bp, 1) // P5_2: TX_MIX_BP
| boot_bit(lpf, 1) // P5_1: LPF
| (0 << 9) // P5_0: Varies by revision
| boot_bit(hpf, 1) // P4_0: HPF
| boot_bit(sgpio_9, 0) // P4_3: SGPIO9, HOST_CAPTURE
| boot_bit(max283x_enable, 1) // P4_6: XCVR_EN, 10K PD
#endif
| (1 << 14) // P5_5: MIXER_RESETX, 10K PU
| boot_bit(led_tx, 1) // P6_12: LED3 (TX)
| (1 << 7) // P5_7: CS_AD
| (1 << 5) // P4_5: RXENABLE
| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
| boot_bit(rffc5072_select, 1) // P5_4: !MIXER_ENX
| boot_bit(rffc5072_resetx, 1) // P5_5: !MIXER_RESETX
| boot_bit(led_tx, 1) // P6_12: LED3 (TX)
| (1 << 7) // P5_7: CS_AD
| (1 << 5) // P4_5: RXENABLE
| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
},
{
// GPIO3
@@ -233,14 +230,15 @@ const PALConfig pal_default_config = {
| (0 << 6) // P6_10: unused on PRALINE
| boot_bit(p1_ctrl2, 0) // P6_9: P1_CTRL2
| boot_bit(aux_power_oc, 0) // P6_11: AUX overcurrent
| boot_bit(sct_clk_in, 0) // P6_4: SCT clock input
#else
| (1 << 4) // P6_5: HackRF CPLD.TMS(I)
| boot_bit(vregmode, 1) // P6_11: VREGMODE
| (0 << 6) // P6_10: Varies by revision
| boot_bit(sgpio_4, 1) // P6_3: SGPIO4
| boot_bit(tx_amp_pwr, 1) // P6_9: !TX_AMP_PWR, 10K PU
| (1 << 4) // P6_5: HackRF CPLD.TMS(I)
| boot_bit(vregmode, 1) // P6_11: VREGMODE
| (0 << 6) // P6_10: Varies by revision
| boot_bit(sgpio_4, 1) // P6_3: SGPIO4
| boot_bit(tx_amp_pwr, 1) // P6_9: !TX_AMP_PWR, 10K PU
| boot_bit(rffc5072_sdata, 0) // P6_4: MIXER_SDATA
#endif
| (1 << 3) // P6_4: MIXER_SDATA
| (1 << 1) // P6_2: HackRF CPLD.TDI(I)
| (1 << 0) // P6_1: HackRF CPLD.TCK(I)
,
@@ -258,14 +256,15 @@ const PALConfig pal_default_config = {
| boot_bit(mix_bypass, 1) // P6_3: MIX_ENABLE_N
| (0 << 6) // P6_10: unused on PRALINE
| boot_bit(p1_ctrl2, 1) // P6_9: P1_CTRL2
| boot_bit(sct_clk_in, 0) // P6_4: SCT clock input
#else
| boot_bit(vregmode, 1) // P6_11: VREGMODE
| (0 << 6) // P6_10: Varies by revision
| boot_bit(sgpio_4, 0) // P6_3: SGPIO4
| boot_bit(tx_amp_pwr, 1) // P6_9: !TX_AMP_PWR, 10K PU
| boot_bit(vregmode, 1) // P6_11: VREGMODE
| (0 << 6) // P6_10: Varies by revision
| boot_bit(sgpio_4, 0) // P6_3: SGPIO4
| boot_bit(tx_amp_pwr, 1) // P6_9: !TX_AMP_PWR, 10K PU
| boot_bit(rffc5072_sdata, 1) // P6_4: MIXER_SDATA
#endif
| (0 << 4) // P6_5: HackRF CPLD.TMS(I)
| (0 << 3) // P6_4: MIXER_SDATA
| (0 << 1) // P6_2: HackRF CPLD.TDI(I)
| (0 << 0) // P6_1: HackRF CPLD.TCK(I)
},
@@ -274,48 +273,48 @@ const PALConfig pal_default_config = {
.data =
boot_bit(sgpio_8, 0) // P9_6: SGPIO8, SGPIO_CLK, PRALINE: P8_0
#ifdef PRALINE
| boot_bit(rf_amp_enable, 0) // PA_2: RF_AMP_EN
| boot_bit(lpf, 0) // PA_1: LPF_EN
| boot_bit(en_1v2, 0) // P8_7: EN_1V2
| boot_bit(led_mcu, 1) // P8_6: LED4
| boot_bit(sgpio_10, 1) // P8_2: SGPIO10, HOST_DISABLE
| (0 << 5) // P8_5: VIN_IN_EN
| (0 << 4) // P8_4: VBUS_IN_EN
| boot_bit(VAA_en, 1) // P8_1: !VAA_EN
| (0 << 10) // PA_3: Output GND
| (0 << 11) // P9_6: MAX2831 LD
| boot_bit(rf5072_mix_en, 0) // P9_0: RF5072 enable
| (0 << 13) // P9_1: Output GND
| (0 << 14) // P9_2: RFFC5072 SDATA
| (0 << 3) // P8_3: Output GND
| boot_bit(sgpio_9, 1) // P9_3: Capture Input
| boot_bit(rf_amp_enable, 0) // PA_2: RF_AMP_EN
| boot_bit(lpf, 0) // PA_1: LPF_EN
| boot_bit(en_1v2, 0) // P8_7: EN_1V2
| boot_bit(led_mcu, 1) // P8_6: LED4
| boot_bit(sgpio_10, 1) // P8_2: SGPIO10, HOST_DISABLE
| (0 << 5) // P8_5: VIN_IN_EN
| (0 << 4) // P8_4: VBUS_IN_EN
| boot_bit(VAA_en, 1) // P8_1: !VAA_EN
| (0 << 10) // PA_3: Output GND
| (0 << 11) // P9_6: MAX2831 LD
| boot_bit(rf5072_mix_en, 0) // P9_0: RF5072 enable
| (0 << 13) // P9_1: Output GND
| boot_bit(rffc5072_sdata, 0) // P9_2: RFFC5072 SDATA
| (0 << 3) // P8_3: Output GND
| boot_bit(sgpio_9, 1) // P9_3: Capture Input
#endif
,
.dir =
boot_bit(sgpio_8, 0) // P9_6: SGPIO8, SGPIO_CLK, PRALINE: P8_0
#ifdef PRALINE
| boot_bit(rf_amp_enable, 1) // PA_2: RF_AMP_EN
| boot_bit(lpf, 1) // PA_1: LPF_EN
| boot_bit(en_1v2, 1) // P8_7: EN_1V2
| boot_bit(led_mcu, 1) // P8_6: LED4
| boot_bit(sgpio_10, 0) // P8_2: SGPIO10, HOST_DISABLE
| (1 << 5) // P8_5: VIN_IN_EN
| (1 << 4) // P8_4: VBUS_IN_EN
| boot_bit(VAA_en, 1) // P8_1: !VAA_EN
| (1 << 10) // PA_3: Output
| (0 << 11) // P9_6: MAX2831 LD
| boot_bit(rf5072_mix_en, 1) // P9_0: RF5072 enable
| (1 << 13) // P9_1: Output
| (0 << 14) // P9_2: RFFC5072 SDATA (Bidirectional)
| (1 << 3) // P8_3: Output
| boot_bit(sgpio_9, 0) // P9_3: Capture Input
| boot_bit(rf_amp_enable, 1) // PA_2: RF_AMP_EN
| boot_bit(lpf, 1) // PA_1: LPF_EN
| boot_bit(en_1v2, 1) // P8_7: EN_1V2
| boot_bit(led_mcu, 1) // P8_6: LED4
| boot_bit(sgpio_10, 0) // P8_2: SGPIO10, HOST_DISABLE
| (1 << 5) // P8_5: VIN_IN_EN
| (1 << 4) // P8_4: VBUS_IN_EN
| boot_bit(VAA_en, 1) // P8_1: !VAA_EN
| (1 << 10) // PA_3: Output
| (0 << 11) // P9_6: MAX2831 LD
| boot_bit(rf5072_mix_en, 1) // P9_0: RF5072 enable
| (1 << 13) // P9_1: Output
| boot_bit(rffc5072_sdata, 1) // P9_2: RFFC5072 SDATA (Bidirectional)
| (1 << 3) // P8_3: Output
| boot_bit(sgpio_9, 0) // P9_3: Capture Input
#endif
},
{
// GPIO5
.data =
#ifdef PRALINE
(0 << 18) // P9_5: RFF5072 SCLK
boot_bit(rffc5072_clock, 0) // P9_5: RFF5072 SCLK
| boot_bit(trigger_out, 0) // P2_6: Trigger out
| (0 << 14) // P4_10: FPGA CDONE
| boot_bit(aux_power_enable, 1) // P6_7: !3V3 AUX_ENABLE
@@ -332,12 +331,12 @@ const PALConfig pal_default_config = {
| (0 << 12) // P4_8: Output GND
| boot_bit(vregmode, 1) // P4_9: TPS62410 VREGMODE
#else
(1 << 18) // P9_5: HackRF CPLD.TDO(O)
| (0 << 6) // P2_6: MIXER_SCLK
| (1 << 14) // P4_10: SGPIO15, CPLD (unused)
| boot_bit(rx_mix_bypass, 1) // P6_8: RX MIX BYPASS
| (1 << 13) // P4_9: SGPIO14, CPLD (unused)
| (0 << 12) // P4_8: Varies by revision
(1 << 18) // P9_5: HackRF CPLD.TDO(O)
| boot_bit(rffc5072_clock, 0) // P2_6: MIXER_SCLK
| (1 << 14) // P4_10: SGPIO15, CPLD (unused)
| boot_bit(rx_mix_bypass, 1) // P6_8: RX MIX BYPASS
| (1 << 13) // P4_9: SGPIO14, CPLD (unused)
| (0 << 12) // P4_8: Varies by revision
#endif
| (1 << 11) // P3_8: SPIFI_CS
| (1 << 10) // P3_7: SPIFI_MOSI
@@ -352,7 +351,7 @@ const PALConfig pal_default_config = {
,
.dir =
#ifdef PRALINE
(1 << 18) // P9_5: RFF5072 SCLK
boot_bit(rffc5072_clock, 1) // P9_5: RFF5072 SCLK
| boot_bit(trigger_out, 1) // P2_6: Trigger out
| (0 << 14) // P4_10: FPGA CDONE
| boot_bit(aux_power_enable, 1) // P6_7: !3V3 AUX_ENABLE
@@ -369,12 +368,12 @@ const PALConfig pal_default_config = {
| (1 << 12) // P4_8: Output
| boot_bit(vregmode, 1) // P4_9: TPS62410 VREGMODE
#else
(0 << 18) // P9_5: HackRF CPLD.TDO(O)
| (1 << 6) // P2_6: MIXER_SCLK
| (0 << 14) // P4_10: SGPIO15, CPLD
| boot_bit(rx_mix_bypass, 1) // P6_8: RX MIX BYPASS
| (0 << 13) // P4_9: SGPIO14, CPLD
| (0 << 12) // P4_8: Varies by revision
(0 << 18) // P9_5: HackRF CPLD.TDO(O)
| boot_bit(rffc5072_clock, 1) // P2_6: MIXER_SCLK
| (0 << 14) // P4_10: SGPIO15, CPLD
| boot_bit(rx_mix_bypass, 1) // P6_8: RX MIX BYPASS
| (0 << 13) // P4_9: SGPIO14, CPLD
| (0 << 12) // P4_8: Varies by revision
#endif
| (0 << 11) // P3_8: SPIFI_CS
| (0 << 10) // P3_7: SPIFI_MOSI
@@ -390,17 +389,17 @@ const PALConfig pal_default_config = {
{
// GPIO6
#ifdef PRALINE
.data = (1 << 28) // PD_14: MAX2831 chip select
| (0 << 29) // PD_15: MAX2831 RXHP control RXHP low = 100 Hz HPF
| (1 << 30) // PD_16: MAX5865 chip select
| (1 << 25) // PD_11: RFFC5072 Lock Detect
| boot_bit(trigger_in, 0) // PD_12: TRIGGER IN
.data = boot_bit(max283x_select, 1) // PD_14: !MAX2831 chip select
| boot_bit(max2831_rxhp, 0) // PD_15: MAX2831 RXHP control RXHP low = 100 Hz HPF
| (1 << 30) // PD_16: MAX5865 chip select
| (1 << 25) // PD_11: RFFC5072 Lock Detect
| boot_bit(trigger_in, 0) // PD_12: TRIGGER IN
,
.dir = (1 << 28) // PD_14: MAX2831 chip select
| (1 << 29) // PD_15: MAX2831 RXHP control
| (1 << 30) // PD_16: MAX5865 chip select
| (0 << 25) // PD_11: RFFC5072 Lock Detect
| boot_bit(trigger_in, 0) // PD_12: TRIGGER IN
.dir = boot_bit(max283x_select, 1) // PD_14: !MAX2831 chip select
| boot_bit(max2831_rxhp, 1) // PD_15: MAX2831 RXHP control
| (1 << 30) // PD_16: MAX5865 chip select
| (0 << 25) // PD_11: RFFC5072 Lock Detect
| boot_bit(trigger_in, 0) // PD_12: TRIGGER IN
#else
.data = 0,
.dir = 0
@@ -409,17 +408,17 @@ const PALConfig pal_default_config = {
{
// GPIO7
#ifdef PRALINE
.data = (0 << 0) // PE_0: Output
| (0 << 1) // PE_1: MAX2831 !SHDN
| (0 << 2) // PE_2: MAX2831 RXTX
| boot_bit(p2_ctrl0, 0) // PE_3: P2_ctrl0
| boot_bit(p2_ctrl1, 0) // PE_4: P2_ctrl1
.data = (0 << 0) // PE_0: Output
| boot_bit(max283x_enable, 0) // PE_1: MAX2831 !SHDN
| boot_bit(max2831_rxtx_enable, 0) // PE_2: MAX2831 RXTX
| boot_bit(p2_ctrl0, 0) // PE_3: P2_ctrl0
| boot_bit(p2_ctrl1, 0) // PE_4: P2_ctrl1
,
.dir = (1 << 0) // PE_0: Output
| (1 << 1) // PE_1: MAX2831 !SHDN
| (1 << 2) // PE_2: MAX2831 RXTX
| boot_bit(p2_ctrl0, 1) // PE_3: P2_ctrl0
| boot_bit(p2_ctrl1, 1) // PE_4: P2_ctrl1
.dir = (1 << 0) // PE_0: Output
| boot_bit(max283x_enable, 1) // PE_1: MAX2831 !SHDN
| boot_bit(max2831_rxtx_enable, 1) // PE_2: MAX2831 RXTX
| boot_bit(p2_ctrl0, 1) // PE_3: P2_ctrl0
| boot_bit(p2_ctrl1, 1) // PE_4: P2_ctrl1
#else
.data = 0,
.dir = 0
@@ -494,7 +493,7 @@ const PALConfig pal_default_config = {
{map_sgpio_12.scu_port, map_sgpio_12.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_12.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO12: HOST_INVERT(I)
#ifdef PRALINE
{6, 4, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // P6_4: SCT_CLK IN (Fast clock input, Mode 1)
{map_sct_clk_in.scu_port, map_sct_clk_in.scu_pin, scu_config_normal_drive_t{.mode = map_sct_clk_in.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // P6_4: SCT_CLK IN (Fast clock input, Mode 1)
{4, 10, scu_config_normal_drive_t{.mode = 7, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P4_10: FPGA Config Done (Input GND)
{map_trigger_in.scu_port, map_trigger_in.scu_pin, scu_config_normal_drive_t{.mode = map_trigger_in.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_12: TRIGGER IN (Input GND, Mode 4)
{map_trigger_out.scu_port, map_trigger_out.scu_pin, scu_config_normal_drive_t{.mode = map_trigger_out.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P2_6: TRIGGER
@@ -504,10 +503,7 @@ const PALConfig pal_default_config = {
{4, 9, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO14/BANK2F3M4: CPLD_P81
{4, 10, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO15/BANK2F3M6: CPLD_P78
{2, 6, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 1}}, // MIXER_SCLK/P31: 33pF, RFFC5072.SCLK(I)
{4, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // RXENABLE
{4, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // XCVR_EN: 10K PD
{1, 20, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_20 CS_XCVR: MAX2837.CS(I)
{map_hpf.scu_port, map_hpf.scu_pin, scu_config_normal_drive_t{.mode = map_hpf.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_0 HPF
{map_rx_amp.scu_port, map_rx_amp.scu_pin, scu_config_normal_drive_t{.mode = map_rx_amp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_11 RX_AMP
{map_rx_amp_pwr.scu_port, map_rx_amp_pwr.scu_pin, scu_config_normal_drive_t{.mode = map_rx_amp_pwr.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_12 !RX_AMP_PWR
@@ -515,43 +511,44 @@ const PALConfig pal_default_config = {
#endif
// RADIO & RF PATH (MAX2831, RFFC5072, Mixers, Switches, Amps)
{1, 3, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P1_3 SSP1_MISO: MAX2837.DOUT(O)
{1, 4, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_4 SSP1_MOSI: MAX2837.DIN(I)
{1, 19, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // P1_19 SSP1_SCK: MAX2837.SCLK(I)
{map_lpf.scu_port, map_lpf.scu_pin, scu_config_normal_drive_t{.mode = map_lpf.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_1 LPF
{1, 3, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P1_3 SSP1_MISO: MAX2837.DOUT(O)
{1, 4, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_4 SSP1_MOSI: MAX2837.DIN(I)
{1, 19, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // P1_19 SSP1_SCK: MAX2837.SCLK(I)
{map_lpf.scu_port, map_lpf.scu_pin, scu_config_normal_drive_t{.mode = map_lpf.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_1 LPF
{map_rffc5072_clock.scu_port, map_rffc5072_clock.scu_pin, scu_config_normal_drive_t{.mode = map_rffc5072_clock.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 1}}, // P2_6: MIXER_SCLK/P31: 33pF, RFFC5072.SCLK(I) PRALINE: P9_5: RFFC5072 SCLK
{map_max283x_select.scu_port, map_max283x_select.scu_pin, scu_config_normal_drive_t{.mode = map_max283x_select.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P1_20 CS_XCVR: MAX2837.CS(I), PRALINE: PD_14: MAX2831 CS
{map_max283x_enable.scu_port, map_max283x_enable.scu_pin, scu_config_normal_drive_t{.mode = map_max283x_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P4_6 max283x enable, PRALINE: PE_1: MAX2831 !SHDN
#ifdef PRALINE
{5, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_4: RFFC ENX
{5, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_5: RFFC RESETX
{9, 5, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // P9_5: RFFC5072 SCLK
{9, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 1, .ezi = 1, .zif = 0}}, // P9_2: RFFC5072 DATA (Bidirectional)
{13, 11, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_11: RFFC Lock Detect
{13, 14, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_14: MAX2831 CS
{13, 15, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PD_15: MAX2831 RXHP
{13, 16, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_16: MAX5864 CS
{14, 1, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PE_1: MAX2831 !SHDN
{14, 2, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PE_2: MAX2831 RXTX
{map_p1_ctrl1.scu_port, map_p1_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl1.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 P1_CTRL1 (Output GND, Mode 4)
{map_aa_en.scu_port, map_aa_en.scu_pin, scu_config_normal_drive_t{.mode = map_aa_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 0}}, // P1_14: AA_EN
{map_rf5072_mix_en.scu_port, map_rf5072_mix_en.scu_pin, scu_config_normal_drive_t{.mode = map_rf5072_mix_en.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_0: RF5072 MIX EN
{9, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_6: MAX2831 LD Input
{map_tx_enable.scu_port, map_tx_enable.scu_pin, scu_config_normal_drive_t{.mode = map_tx_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_5: TX enable
{10, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_1: LPF enable
{10, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_2: RF amp enable
{map_mix_bypass.scu_port, map_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_mix_bypass.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_3: MIX_ENABLE_N
{map_rf_amp_enable.scu_port, map_rf_amp_enable.scu_pin, scu_config_normal_drive_t{.mode = map_rf_amp_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PA_2 RF_AMP_EN
{13, 11, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_11: RFFC Lock Detect
{map_max2831_rxhp.scu_port, map_max2831_rxhp.scu_pin, scu_config_normal_drive_t{.mode = map_max2831_rxhp.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PD_15: MAX2831 RXHP
{13, 16, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_16: MAX5864 CS
{map_max2831_rxtx_enable.scu_port, map_max2831_rxtx_enable.scu_pin, scu_config_normal_drive_t{.mode = map_max2831_rxtx_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PE_2: MAX2831 RXTX
{map_p1_ctrl1.scu_port, map_p1_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl1.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 P1_CTRL1 (Output GND, Mode 4)
{map_aa_en.scu_port, map_aa_en.scu_pin, scu_config_normal_drive_t{.mode = map_aa_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 0}}, // P1_14: AA_EN
{map_rf5072_mix_en.scu_port, map_rf5072_mix_en.scu_pin, scu_config_normal_drive_t{.mode = map_rf5072_mix_en.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_0: RF5072 MIX EN
{9, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_6: MAX2831 LD Input
{map_tx_enable.scu_port, map_tx_enable.scu_pin, scu_config_normal_drive_t{.mode = map_tx_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_5: TX enable
{10, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_1: LPF enable
{10, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_2: RF amp enable
{map_mix_bypass.scu_port, map_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_mix_bypass.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_3: MIX_ENABLE_N
{map_rf_amp_enable.scu_port, map_rf_amp_enable.scu_pin, scu_config_normal_drive_t{.mode = map_rf_amp_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PA_2 RF_AMP_EN
#else
{map_rx_mix_bp.scu_port, map_rx_mix_bp.scu_pin, scu_config_normal_drive_t{.mode = map_rx_mix_bp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_3 RX_MIX_BP
{5, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_ENX
{map_tx_amp.scu_port, map_tx_amp.scu_pin, scu_config_normal_drive_t{.mode = map_tx_amp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_6 TX_AMP
{5, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_7 CS_AD, PRALINE: RFFC5072 CS
{5, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_RESETX
{6, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // MIXER_SDATA
{map_rx_mix_bp.scu_port, map_rx_mix_bp.scu_pin, scu_config_normal_drive_t{.mode = map_rx_mix_bp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_3 RX_MIX_BP
{map_tx_amp.scu_port, map_tx_amp.scu_pin, scu_config_normal_drive_t{.mode = map_tx_amp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_6 TX_AMP
{5, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_7 CS_AD, PRALINE: RFFC5072 CS
{map_tx_mix_bypass.scu_port, map_tx_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_tx_mix_bypass.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 !TX MIX BYPASS
{map_amp_bypass.scu_port, map_amp_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_amp_bypass.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_10 AMP_BYPASS
{map_tx_amp_pwr.scu_port, map_tx_amp_pwr.scu_pin, scu_config_normal_drive_t{.mode = map_tx_amp_pwr.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // !TX_AMP_PWR
{map_rx_mix_bypass.scu_port, map_rx_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_rx_mix_bypass.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_8 RX MIX BYPASS
#endif
{map_rffc5072_select.scu_port, map_rffc5072_select.scu_pin, scu_config_normal_drive_t{.mode = map_rffc5072_select.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_4: MIXER_ENX
{map_rffc5072_resetx.scu_port, map_rffc5072_resetx.scu_pin, scu_config_normal_drive_t{.mode = map_rffc5072_resetx.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_RESETX
{map_rffc5072_sdata.scu_port, map_rffc5072_sdata.scu_pin, scu_config_normal_drive_t{.mode = map_rffc5072_sdata.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 1, .zif = 0}}, // P6_4: RFFC5072 DATA (Bidirectional) PRALINE P9_2
// SAFE TERMINATION (Unused pins grounded to prevent noise & save power)
#ifdef PRALINE
@@ -584,7 +581,7 @@ const PALConfig pal_default_config = {
{map_isp.scu_port, map_isp.scu_pin, scu_config_normal_drive_t{.mode = map_isp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_7: ISP: 10K PU, Unused
{map_dfu_boot_0.scu_port, map_dfu_boot_0.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_boot_0.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_1: 10K PU, BOOT0
{map_dfu_boot_1.scu_port, map_dfu_boot_1.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_boot_1.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_2: 10K PD, BOOT1
{map_dfu_button.scu_port, map_dfu_button.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_button.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 1}}, // P2_8: BOOT2, DFU button
{map_dfu_button.scu_port, map_dfu_button.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_button.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 1}}, // P2_8: 10K PD, BOOT2, DFU button
{map_lcd_wrx.scu_port, map_lcd_wrx.scu_pin, scu_config_normal_drive_t{.mode = map_lcd_wrx.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
}};
firmware/common/gpio.hpp
+49
View File
@@ -394,6 +394,17 @@ constexpr PinMap map_lpf{10, 1, 4, 8, 4};
constexpr PinMap map_tx_enable{6, 5, 3, 4, 0};
constexpr PinMap map_rf_amp_enable{10, 2, 4, 9, 0};
constexpr PinMap map_pps_in_out{2, 5, 5, 5, 4};
constexpr PinMap map_rffc5072_clock{9, 5, 5, 18, 4};
constexpr PinMap map_rffc5072_sdata{9, 2, 4, 14, 0};
constexpr PinMap map_sct_clk_in{6, 4, 3, 3, 1};
constexpr PinMap map_max283x_select{13, 14, 6, 28, 4};
constexpr PinMap map_max283x_enable{14, 1, 7, 1, 4};
constexpr PinMap map_max2831_rxtx_enable{14, 2, 7, 2, 4};
constexpr PinMap map_max2831_rxhp{13, 15, 6, 29, 4};
// constexpr PinMap map_unused_1{2, 7, 0, 7, 0};
#else
@@ -425,6 +436,13 @@ constexpr PinMap map_ant_bias{4, 4, 2, 4, 0};
constexpr PinMap map_r9_mcu_clk_en{1, 1, 0, 8, 0};
constexpr PinMap map_r9_clkout_en{1, 2, 0, 9, 0};
constexpr PinMap map_r9_clkin_en{6, 7, 5, 15, 4};
constexpr PinMap map_rffc5072_clock{2, 6, 5, 6, 4};
constexpr PinMap map_rffc5072_sdata{6, 4, 3, 3, 0};
constexpr PinMap map_max283x_select{1, 20, 0, 15, 0};
constexpr PinMap map_max283x_enable{4, 6, 2, 6, 0};
#endif
constexpr PinMap map_sgpio_0{0, 0, 0, 0, 3};
@@ -445,6 +463,10 @@ constexpr PinMap map_dfu_boot_1{1, 2, 0, 9, 0};
constexpr PinMap map_dfu_button{2, 8, 5, 7, 4};
constexpr PinMap map_lcd_wrx{2, 9, 1, 10, 0};
constexpr PinMap map_isp{2, 7, 0, 7, 0};
constexpr PinMap map_rffc5072_select{5, 4, 2, 13, 0};
constexpr PinMap map_rffc5072_resetx{5, 5, 2, 14, 0};
#ifdef PRALINE
// P1 Multiplexer control pins
@@ -522,6 +544,15 @@ constexpr GPIO ant_bias_oc{pin_ant_bias_oc, map_ant_bias_oc.gpio_port, map_ant_b
constexpr Pin pin_pps_in_out{map_pps_in_out.scu_port, map_pps_in_out.scu_pin}; // SCU: P2_5
constexpr GPIO pps_in_out{pin_pps_in_out, map_pps_in_out.gpio_port, map_pps_in_out.gpio_pad, map_pps_in_out.gpio_mode}; // GPIO[5]5
constexpr Pin pin_sct_clk_in{map_sct_clk_in.scu_port, map_sct_clk_in.scu_pin}; // SCU: P6_4
constexpr GPIO sct_clk_in{pin_sct_clk_in, map_sct_clk_in.gpio_port, map_sct_clk_in.gpio_pad, map_sct_clk_in.gpio_mode}; // GPIO[3]3
constexpr Pin pin_max2831_rxtx_enable{map_max2831_rxtx_enable.scu_port, map_max2831_rxtx_enable.scu_pin}; // SCU: PE_2
constexpr GPIO max2831_rxtx_enable{pin_max2831_rxtx_enable, map_max2831_rxtx_enable.gpio_port, map_max2831_rxtx_enable.gpio_pad, map_max2831_rxtx_enable.gpio_mode}; // GPIO[7]2
constexpr Pin pin_max2831_rxhp{map_max2831_rxhp.scu_port, map_max2831_rxhp.scu_pin}; // SCU: PD_15
constexpr GPIO max2831_rxhp{pin_max2831_rxhp, map_max2831_rxhp.gpio_port, map_max2831_rxhp.gpio_pad, map_max2831_rxhp.gpio_mode}; // GPIO[6]29
#else
constexpr Pin pin_sgpio_13{map_sgpio_13.scu_port, map_sgpio_13.scu_pin}; // SCU: P4_8
constexpr GPIO sgpio_13{pin_sgpio_13, map_sgpio_13.gpio_port, map_sgpio_13.gpio_pad, map_sgpio_13.gpio_mode}; // GPIO[5]12
@@ -671,6 +702,24 @@ constexpr GPIO lcd_wrx{pin_lcd_wrx, map_lcd_wrx.gpio_port, map_lcd_wrx.gpio_pad,
constexpr Pin pin_isp{map_isp.scu_port, map_isp.scu_pin}; // SCU: P2_7
constexpr GPIO dfu_isp{pin_isp, map_isp.gpio_port, map_isp.gpio_pad, map_isp.gpio_mode}; // GPIO[0]7
constexpr Pin pin_rffc5072_clock{map_rffc5072_clock.scu_port, map_rffc5072_clock.scu_pin}; // SCU: P2_6, PRALINE: P9_5
constexpr GPIO rffc5072_clock{pin_rffc5072_clock, map_rffc5072_clock.gpio_port, map_rffc5072_clock.gpio_pad, map_rffc5072_clock.gpio_mode}; // GPIO[5]6, PRALINE: GPIO[5]18
constexpr Pin pin_rffc5072_sdata{map_rffc5072_sdata.scu_port, map_rffc5072_sdata.scu_pin}; // SCU: P6_4, PRALINE: P9_2
constexpr GPIO rffc5072_sdata{pin_rffc5072_sdata, map_rffc5072_sdata.gpio_port, map_rffc5072_sdata.gpio_pad, map_rffc5072_sdata.gpio_mode}; // GPIO[3]3, PRALINE: GPIO[4]14
constexpr Pin pin_rffc5072_select{map_rffc5072_select.scu_port, map_rffc5072_select.scu_pin}; // SCU: P5_4
constexpr GPIO rffc5072_select{pin_rffc5072_select, map_rffc5072_select.gpio_port, map_rffc5072_select.gpio_pad, map_rffc5072_select.gpio_mode, Polarity::ActiveLow}; // GPIO[2]13
constexpr Pin pin_rffc5072_resetx{map_rffc5072_resetx.scu_port, map_rffc5072_resetx.scu_pin}; // SCU: P5_5
constexpr GPIO rffc5072_resetx{pin_rffc5072_resetx, map_rffc5072_resetx.gpio_port, map_rffc5072_resetx.gpio_pad, map_rffc5072_resetx.gpio_mode, Polarity::ActiveLow}; // GPIO[2]14
constexpr Pin pin_max283x_select{map_max283x_select.scu_port, map_max283x_select.scu_pin}; // SCU: P1_20, PRALINE: PD_14
constexpr GPIO max283x_select{pin_max283x_select, map_max283x_select.gpio_port, map_max283x_select.gpio_pad, map_max283x_select.gpio_mode, Polarity::ActiveLow}; // GPIO[0]15, PRALINE: GPIO[6]28
constexpr Pin pin_max283x_enable{map_max283x_enable.scu_port, map_max283x_enable.scu_pin}; // SCU: P4_6, PRALINE: PE_1
constexpr GPIO max283x_enable{pin_max283x_enable, map_max283x_enable.gpio_port, map_max283x_enable.gpio_pad, map_max283x_enable.gpio_mode}; // GPIO[2]6, PRALINE: GPIO[7]1
} // namespace gpio_control
namespace power_control {
firmware/common/hackrf_gpio.hpp
+2 -32
View File
@@ -34,41 +34,11 @@ namespace one {
/* GPIO */
#ifdef PRALINE
// PRALINE: GPIO2[13] is SPI CS only, FPGA controls ENX/RESETX
constexpr GPIO gpio_rffc5072_select = gpio[GPIO2_13]; // P5_4: SPI CS (ENX)
constexpr GPIO gpio_rffc5072_resetx = gpio[GPIO2_14]; // P5_5: LPC43xx controls directly
#else
constexpr GPIO gpio_rffc5072_select = gpio[GPIO2_13];
constexpr GPIO gpio_rffc5072_resetx = gpio[GPIO2_14];
#endif
#ifdef PRALINE
constexpr GPIO gpio_rffc5072_clock = gpio[GPIO5_18];
constexpr GPIO gpio_rffc5072_data = gpio[GPIO4_14];
#else
constexpr GPIO gpio_rffc5072_clock = gpio[GPIO5_6];
constexpr GPIO gpio_rffc5072_data = gpio[GPIO3_3];
#endif
#ifdef PRALINE
constexpr GPIO gpio_max283x_select = gpio[GPIO6_28];
#else
constexpr GPIO gpio_max283x_select = gpio[GPIO0_15];
#endif
#ifdef PRALINE
// PRALINE uses MAX2831 transceiver with different control pins
constexpr GPIO gpio_max283x_enable = gpio[GPIO7_1]; // MAX2831 ENABLE (PE_1)
// constexpr GPIO gpio_max2831_enable = gpio[GPIO7_1]; // Alias
constexpr GPIO gpio_max2831_rx_enable = gpio[GPIO7_2]; // MAX2831 RX_ENABLE (PE_2)
// constexpr GPIO gpio_max2831_rxhp = gpio[GPIO6_29]; // MAX2831 RXHP (PD_15)
constexpr GPIO gpio_max2831_ld = gpio[GPIO4_11]; // MAX2831 Lock Detect (P9_6)
// Legacy aliases for code compatibility
constexpr GPIO gpio_max2837_rxenable = gpio[GPIO7_2];
constexpr GPIO gpio_max2837_txenable = gpio[GPIO7_2]; // MAX2831 uses single RX/TX control
constexpr GPIO gpio_max2839_rxtx = gpio[GPIO7_2];
#else
constexpr GPIO gpio_max283x_enable = gpio[GPIO2_6];
constexpr GPIO gpio_max2837_rxenable = gpio[GPIO2_5];
constexpr GPIO gpio_max2837_txenable = gpio[GPIO2_4];
constexpr GPIO gpio_max2839_rxtx = gpio[GPIO2_5];
firmware/common/portapack_hal.hpp
+5 -7
View File
@@ -33,13 +33,11 @@ namespace portapack {
/* TODO: Make these GPIOs private and expose via appropriate functions. */
constexpr GPIO gpio_io_stbx = gpio[GPIO5_0]; /* P2_0 */
constexpr GPIO gpio_addr = gpio[GPIO5_1]; /* P2_1 */
constexpr GPIO gpio_lcd_te = gpio[GPIO5_3]; /* P2_3 */
constexpr GPIO gpio_dfu = gpio[GPIO5_7]; /* P2_8 */
constexpr GPIO gpio_lcd_rdx = gpio[GPIO5_4]; /* P2_4 */
constexpr GPIO gpio_lcd_wrx = gpio[GPIO1_10]; /* P2_9 */
constexpr GPIO gpio_dir = gpio[GPIO1_13]; /* P2_13 */
constexpr GPIO gpio_io_stbx = gpio[GPIO5_0]; /* P2_0 */
constexpr GPIO gpio_addr = gpio[GPIO5_1]; /* P2_1 */
constexpr GPIO gpio_lcd_te = gpio[GPIO5_3]; /* P2_3 */
constexpr GPIO gpio_lcd_rdx = gpio[GPIO5_4]; /* P2_4 */
constexpr GPIO gpio_dir = gpio[GPIO1_13]; /* P2_13 */
constexpr std::array<GPIO, 8> gpios_data{
gpio[GPIO3_8],
gpio[GPIO3_9],
firmware/common/portapack_io.cpp
+1 -3
View File
@@ -82,11 +82,9 @@ void IO::init() {
gpio_dir.output();
gpio_lcd_rdx.output();
gpio_lcd_wrx.output();
gpio_io_stbx.output();
gpio_addr.output();
gpio_rot_a.input();
gpio_rot_b.input();
}
void IO::lcd_backlight(const bool value) {
@@ -166,7 +164,7 @@ uint32_t IO::io_update(const TouchPinsConfig write_value) {
}
gpio_addr.write(addr);
auto dfu_btn = portapack::io.dfu_read() & 0x01;
uint32_t dfu_btn = gpio_control::dfu_button.read();
return (switches_raw & 0x7f) | (dfu_btn << 7);
}
firmware/common/portapack_io.hpp
+6 -14
View File
@@ -33,6 +33,8 @@
#include "gpio.hpp"
#include "ui.hpp"
#include "gpio.hpp"
// #include "portapack_persistent_memory.hpp"
// Darkened pixel bit mask for each possible shift value.
@@ -108,18 +110,14 @@ class IO {
constexpr IO(
GPIO gpio_dir,
GPIO gpio_lcd_rdx,
GPIO gpio_lcd_wrx,
GPIO gpio_io_stbx,
GPIO gpio_addr,
GPIO gpio_rot_a,
GPIO gpio_rot_b)
GPIO gpio_rot_a)
: gpio_dir{gpio_dir},
gpio_lcd_rdx{gpio_lcd_rdx},
gpio_lcd_wrx{gpio_lcd_wrx},
gpio_io_stbx{gpio_io_stbx},
gpio_addr{gpio_addr},
gpio_rot_a{gpio_rot_a},
gpio_rot_b{gpio_rot_b} {};
gpio_rot_a{gpio_rot_a} {};
void init();
@@ -270,18 +268,12 @@ class IO {
return gpio_rot_a.read();
}
uint32_t dfu_read() {
return gpio_rot_b.read();
}
private:
const GPIO gpio_dir;
const GPIO gpio_lcd_rdx;
const GPIO gpio_lcd_wrx;
const GPIO gpio_io_stbx;
const GPIO gpio_addr;
const GPIO gpio_rot_a;
const GPIO gpio_rot_b;
static constexpr ioportid_t gpio_data_port_id = 3;
static constexpr size_t gpio_data_shift = 8;
@@ -298,11 +290,11 @@ class IO {
}
void lcd_wr_assert() {
gpio_lcd_wrx.clear();
gpio_control::lcd_wrx.setInactive();
}
void lcd_wr_deassert() {
gpio_lcd_wrx.set();
gpio_control::lcd_wrx.setActive();
}
void io_stb_assert() {