mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-09-10 16:49:36 +00:00
Gpio modify v4 (#3266)
* Refactor GPIO handling for RFFC5072: update pin mappings and simplify initialization * Refactor GPIO handling: replace portapack::gpio_dfu with dfu_button and clean up unused GPIOs * Refactor MAX283x GPIO handling: update pin mappings and simplify initialization * Refactor GPIO handling: update MAX2831 shutdown pin configuration * Refactor GPIO handling: add MAX2831 RXHP and RXTX control, update related configurations * Refactor MAX2831 frequency setting to include reference divider parameter and improve validation checks * Refactor MAX2831 frequency setting to remove reference divider parameter and improve frequency validation * copilot
This commit is contained in:
Pezsma
GitHub
@@ -60,8 +60,8 @@ const PALConfig pal_default_config = {
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= boot_bit(p1_ctrl0, 0) // P2_10: P1_CTRL0, start low
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| boot_bit(clkin_ctrl, 0) // P1_20: CLKIN_CTRL - start low
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#else
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= boot_bit(amp_bypass, 1) // P2_10: AMP_BYPASS
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| (1 << 15) // P1_20: CS_XCVR
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= boot_bit(amp_bypass, 1) // P2_10: AMP_BYPASS
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| boot_bit(max283x_select, 1) // P1_20: !CS_XCVR
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#endif
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| boot_bit(dfu_boot_0, 0) // P1_1: 10K PU, BOOT0
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| boot_bit(dfu_boot_1, 0) // P1_2: 10K PD, BOOT1
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@@ -83,8 +83,8 @@ const PALConfig pal_default_config = {
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= boot_bit(p1_ctrl0, 1) // P2_10: P1_CTRL0
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| boot_bit(clkin_ctrl, 1) // P1_20: CLKIN_CTRL
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#else
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= boot_bit(amp_bypass, 1) // P2_10: AMP_BYPASS
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| (1 << 15) // P1_20: CS_XCVR
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= boot_bit(amp_bypass, 1) // P2_10: AMP_BYPASS
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| boot_bit(max283x_select, 1) // P1_20: !CS_XCVR
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#endif
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| boot_bit(dfu_boot_0, 0) // P1_1: 10K PU, BOOT0
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| boot_bit(dfu_boot_1, 0) // P1_2: 10K PD, BOOT1
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@@ -153,10 +153,9 @@ const PALConfig pal_default_config = {
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},
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{
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// GPIO2
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.data = (1 << 14) // P5_5: MIXER_RESETX, 10K PU
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.data = boot_bit(rffc5072_resetx, 1) // P5_5: !MIXER_RESETX
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#ifdef PRALINE
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| (0 << 15) // P5_6: unused on PRALINE
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| (1 << 13) // P5_4: RFFC5072 ENX
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| (0 << 12) // P5_3: unused on PRALINE
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| (0 << 11) // P5_2: FPGA_CRESET
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| (1 << 10) // P5_1: FPGA_SPI_CS
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@@ -169,9 +168,7 @@ const PALConfig pal_default_config = {
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| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
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| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
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#else
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| boot_bit(tx_amp, 0) // P5_6: TX_AMP
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| (1 << 13) // P5_4: MIXER_ENX, 10K PU
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| boot_bit(tx_amp, 0) // P5_6: TX_AMP
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| boot_bit(rx_mix_bp, 1) // P5_3: RX_MIX_BP
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| boot_bit(tx_mix_bp, 0) // P5_2: TX_MIX_BP
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| boot_bit(lpf, 0) // P5_1: LPF
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@@ -184,13 +181,13 @@ const PALConfig pal_default_config = {
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| boot_bit(led_usb, 0) // P4_1: LED1 (USB)
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#endif
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| (1 << 7) // P5_7: CS_AD
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| (0 << 5) // P4_5: RXENABLE
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| boot_bit(rffc5072_select, 1) // P5_4: !MIXER_ENX
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| (1 << 7) // P5_7: CS_AD
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| (0 << 5) // P4_5: RXENABLE
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,
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.dir =
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#ifdef PRALINE
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(1 << 15) // P5_6: unused on PRALINE
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| (1 << 13) // P5_4: RFFC5072 ENX
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| (1 << 12) // P5_3: unused on PRALINE
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| (1 << 11) // P5_2: FPGA_CRESET
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| (1 << 10) // P5_1: FPGA_SPI_CS
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@@ -200,22 +197,22 @@ const PALConfig pal_default_config = {
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| (0 << 3) // P4_3: VBUSCTRL input
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| (0 << 6) // P4_6: Input
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#else
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boot_bit(tx_amp, 1) // P5_6: TX_AMP
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| (1 << 13) // P5_4: MIXER_ENX, 10K PU
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| boot_bit(rx_mix_bp, 1) // P5_3: RX_MIX_BP
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| boot_bit(tx_mix_bp, 1) // P5_2: TX_MIX_BP
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| boot_bit(lpf, 1) // P5_1: LPF
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| (0 << 9) // P5_0: Varies by revision
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| boot_bit(hpf, 1) // P4_0: HPF
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| boot_bit(sgpio_9, 0) // P4_3: SGPIO9, HOST_CAPTURE
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| (1 << 6) // P4_6: XCVR_EN, 10K PD
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boot_bit(tx_amp, 1) // P5_6: TX_AMP
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| boot_bit(rx_mix_bp, 1) // P5_3: RX_MIX_BP
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| boot_bit(tx_mix_bp, 1) // P5_2: TX_MIX_BP
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| boot_bit(lpf, 1) // P5_1: LPF
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| (0 << 9) // P5_0: Varies by revision
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| boot_bit(hpf, 1) // P4_0: HPF
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| boot_bit(sgpio_9, 0) // P4_3: SGPIO9, HOST_CAPTURE
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| boot_bit(max283x_enable, 1) // P4_6: XCVR_EN, 10K PD
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#endif
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| (1 << 14) // P5_5: MIXER_RESETX, 10K PU
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| boot_bit(led_tx, 1) // P6_12: LED3 (TX)
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| (1 << 7) // P5_7: CS_AD
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| (1 << 5) // P4_5: RXENABLE
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| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
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| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
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| boot_bit(rffc5072_select, 1) // P5_4: !MIXER_ENX
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| boot_bit(rffc5072_resetx, 1) // P5_5: !MIXER_RESETX
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| boot_bit(led_tx, 1) // P6_12: LED3 (TX)
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| (1 << 7) // P5_7: CS_AD
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| (1 << 5) // P4_5: RXENABLE
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| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
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| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
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},
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{
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// GPIO3
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@@ -233,14 +230,15 @@ const PALConfig pal_default_config = {
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| (0 << 6) // P6_10: unused on PRALINE
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| boot_bit(p1_ctrl2, 0) // P6_9: P1_CTRL2
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| boot_bit(aux_power_oc, 0) // P6_11: AUX overcurrent
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| boot_bit(sct_clk_in, 0) // P6_4: SCT clock input
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#else
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| (1 << 4) // P6_5: HackRF CPLD.TMS(I)
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| boot_bit(vregmode, 1) // P6_11: VREGMODE
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| (0 << 6) // P6_10: Varies by revision
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| boot_bit(sgpio_4, 1) // P6_3: SGPIO4
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| boot_bit(tx_amp_pwr, 1) // P6_9: !TX_AMP_PWR, 10K PU
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| (1 << 4) // P6_5: HackRF CPLD.TMS(I)
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| boot_bit(vregmode, 1) // P6_11: VREGMODE
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| (0 << 6) // P6_10: Varies by revision
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| boot_bit(sgpio_4, 1) // P6_3: SGPIO4
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| boot_bit(tx_amp_pwr, 1) // P6_9: !TX_AMP_PWR, 10K PU
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| boot_bit(rffc5072_sdata, 0) // P6_4: MIXER_SDATA
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#endif
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| (1 << 3) // P6_4: MIXER_SDATA
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| (1 << 1) // P6_2: HackRF CPLD.TDI(I)
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| (1 << 0) // P6_1: HackRF CPLD.TCK(I)
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,
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@@ -258,14 +256,15 @@ const PALConfig pal_default_config = {
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| boot_bit(mix_bypass, 1) // P6_3: MIX_ENABLE_N
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| (0 << 6) // P6_10: unused on PRALINE
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| boot_bit(p1_ctrl2, 1) // P6_9: P1_CTRL2
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| boot_bit(sct_clk_in, 0) // P6_4: SCT clock input
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#else
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| boot_bit(vregmode, 1) // P6_11: VREGMODE
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| (0 << 6) // P6_10: Varies by revision
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| boot_bit(sgpio_4, 0) // P6_3: SGPIO4
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| boot_bit(tx_amp_pwr, 1) // P6_9: !TX_AMP_PWR, 10K PU
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| boot_bit(vregmode, 1) // P6_11: VREGMODE
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| (0 << 6) // P6_10: Varies by revision
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| boot_bit(sgpio_4, 0) // P6_3: SGPIO4
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| boot_bit(tx_amp_pwr, 1) // P6_9: !TX_AMP_PWR, 10K PU
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| boot_bit(rffc5072_sdata, 1) // P6_4: MIXER_SDATA
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#endif
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| (0 << 4) // P6_5: HackRF CPLD.TMS(I)
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| (0 << 3) // P6_4: MIXER_SDATA
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| (0 << 1) // P6_2: HackRF CPLD.TDI(I)
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| (0 << 0) // P6_1: HackRF CPLD.TCK(I)
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},
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@@ -274,48 +273,48 @@ const PALConfig pal_default_config = {
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.data =
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boot_bit(sgpio_8, 0) // P9_6: SGPIO8, SGPIO_CLK, PRALINE: P8_0
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#ifdef PRALINE
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| boot_bit(rf_amp_enable, 0) // PA_2: RF_AMP_EN
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| boot_bit(lpf, 0) // PA_1: LPF_EN
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| boot_bit(en_1v2, 0) // P8_7: EN_1V2
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| boot_bit(led_mcu, 1) // P8_6: LED4
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| boot_bit(sgpio_10, 1) // P8_2: SGPIO10, HOST_DISABLE
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| (0 << 5) // P8_5: VIN_IN_EN
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| (0 << 4) // P8_4: VBUS_IN_EN
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| boot_bit(VAA_en, 1) // P8_1: !VAA_EN
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| (0 << 10) // PA_3: Output GND
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| (0 << 11) // P9_6: MAX2831 LD
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| boot_bit(rf5072_mix_en, 0) // P9_0: RF5072 enable
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| (0 << 13) // P9_1: Output GND
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| (0 << 14) // P9_2: RFFC5072 SDATA
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| (0 << 3) // P8_3: Output GND
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| boot_bit(sgpio_9, 1) // P9_3: Capture Input
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| boot_bit(rf_amp_enable, 0) // PA_2: RF_AMP_EN
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| boot_bit(lpf, 0) // PA_1: LPF_EN
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| boot_bit(en_1v2, 0) // P8_7: EN_1V2
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| boot_bit(led_mcu, 1) // P8_6: LED4
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| boot_bit(sgpio_10, 1) // P8_2: SGPIO10, HOST_DISABLE
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| (0 << 5) // P8_5: VIN_IN_EN
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| (0 << 4) // P8_4: VBUS_IN_EN
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| boot_bit(VAA_en, 1) // P8_1: !VAA_EN
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| (0 << 10) // PA_3: Output GND
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| (0 << 11) // P9_6: MAX2831 LD
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| boot_bit(rf5072_mix_en, 0) // P9_0: RF5072 enable
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| (0 << 13) // P9_1: Output GND
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| boot_bit(rffc5072_sdata, 0) // P9_2: RFFC5072 SDATA
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| (0 << 3) // P8_3: Output GND
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| boot_bit(sgpio_9, 1) // P9_3: Capture Input
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#endif
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,
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.dir =
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boot_bit(sgpio_8, 0) // P9_6: SGPIO8, SGPIO_CLK, PRALINE: P8_0
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#ifdef PRALINE
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| boot_bit(rf_amp_enable, 1) // PA_2: RF_AMP_EN
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| boot_bit(lpf, 1) // PA_1: LPF_EN
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| boot_bit(en_1v2, 1) // P8_7: EN_1V2
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| boot_bit(led_mcu, 1) // P8_6: LED4
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| boot_bit(sgpio_10, 0) // P8_2: SGPIO10, HOST_DISABLE
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| (1 << 5) // P8_5: VIN_IN_EN
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| (1 << 4) // P8_4: VBUS_IN_EN
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| boot_bit(VAA_en, 1) // P8_1: !VAA_EN
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| (1 << 10) // PA_3: Output
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| (0 << 11) // P9_6: MAX2831 LD
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| boot_bit(rf5072_mix_en, 1) // P9_0: RF5072 enable
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| (1 << 13) // P9_1: Output
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| (0 << 14) // P9_2: RFFC5072 SDATA (Bidirectional)
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| (1 << 3) // P8_3: Output
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| boot_bit(sgpio_9, 0) // P9_3: Capture Input
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| boot_bit(rf_amp_enable, 1) // PA_2: RF_AMP_EN
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| boot_bit(lpf, 1) // PA_1: LPF_EN
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| boot_bit(en_1v2, 1) // P8_7: EN_1V2
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| boot_bit(led_mcu, 1) // P8_6: LED4
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| boot_bit(sgpio_10, 0) // P8_2: SGPIO10, HOST_DISABLE
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| (1 << 5) // P8_5: VIN_IN_EN
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| (1 << 4) // P8_4: VBUS_IN_EN
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| boot_bit(VAA_en, 1) // P8_1: !VAA_EN
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| (1 << 10) // PA_3: Output
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| (0 << 11) // P9_6: MAX2831 LD
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| boot_bit(rf5072_mix_en, 1) // P9_0: RF5072 enable
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| (1 << 13) // P9_1: Output
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| boot_bit(rffc5072_sdata, 1) // P9_2: RFFC5072 SDATA (Bidirectional)
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| (1 << 3) // P8_3: Output
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| boot_bit(sgpio_9, 0) // P9_3: Capture Input
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#endif
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},
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{
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// GPIO5
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.data =
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#ifdef PRALINE
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(0 << 18) // P9_5: RFF5072 SCLK
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boot_bit(rffc5072_clock, 0) // P9_5: RFF5072 SCLK
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| boot_bit(trigger_out, 0) // P2_6: Trigger out
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| (0 << 14) // P4_10: FPGA CDONE
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| boot_bit(aux_power_enable, 1) // P6_7: !3V3 AUX_ENABLE
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@@ -332,12 +331,12 @@ const PALConfig pal_default_config = {
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| (0 << 12) // P4_8: Output GND
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| boot_bit(vregmode, 1) // P4_9: TPS62410 VREGMODE
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#else
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(1 << 18) // P9_5: HackRF CPLD.TDO(O)
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| (0 << 6) // P2_6: MIXER_SCLK
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| (1 << 14) // P4_10: SGPIO15, CPLD (unused)
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| boot_bit(rx_mix_bypass, 1) // P6_8: RX MIX BYPASS
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| (1 << 13) // P4_9: SGPIO14, CPLD (unused)
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| (0 << 12) // P4_8: Varies by revision
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(1 << 18) // P9_5: HackRF CPLD.TDO(O)
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| boot_bit(rffc5072_clock, 0) // P2_6: MIXER_SCLK
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| (1 << 14) // P4_10: SGPIO15, CPLD (unused)
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| boot_bit(rx_mix_bypass, 1) // P6_8: RX MIX BYPASS
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| (1 << 13) // P4_9: SGPIO14, CPLD (unused)
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| (0 << 12) // P4_8: Varies by revision
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#endif
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| (1 << 11) // P3_8: SPIFI_CS
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| (1 << 10) // P3_7: SPIFI_MOSI
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@@ -352,7 +351,7 @@ const PALConfig pal_default_config = {
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,
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.dir =
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#ifdef PRALINE
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(1 << 18) // P9_5: RFF5072 SCLK
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boot_bit(rffc5072_clock, 1) // P9_5: RFF5072 SCLK
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| boot_bit(trigger_out, 1) // P2_6: Trigger out
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| (0 << 14) // P4_10: FPGA CDONE
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| boot_bit(aux_power_enable, 1) // P6_7: !3V3 AUX_ENABLE
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@@ -369,12 +368,12 @@ const PALConfig pal_default_config = {
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| (1 << 12) // P4_8: Output
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| boot_bit(vregmode, 1) // P4_9: TPS62410 VREGMODE
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#else
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(0 << 18) // P9_5: HackRF CPLD.TDO(O)
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| (1 << 6) // P2_6: MIXER_SCLK
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| (0 << 14) // P4_10: SGPIO15, CPLD
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| boot_bit(rx_mix_bypass, 1) // P6_8: RX MIX BYPASS
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| (0 << 13) // P4_9: SGPIO14, CPLD
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| (0 << 12) // P4_8: Varies by revision
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(0 << 18) // P9_5: HackRF CPLD.TDO(O)
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| boot_bit(rffc5072_clock, 1) // P2_6: MIXER_SCLK
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| (0 << 14) // P4_10: SGPIO15, CPLD
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| boot_bit(rx_mix_bypass, 1) // P6_8: RX MIX BYPASS
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| (0 << 13) // P4_9: SGPIO14, CPLD
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| (0 << 12) // P4_8: Varies by revision
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#endif
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| (0 << 11) // P3_8: SPIFI_CS
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| (0 << 10) // P3_7: SPIFI_MOSI
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@@ -390,17 +389,17 @@ const PALConfig pal_default_config = {
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{
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// GPIO6
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#ifdef PRALINE
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.data = (1 << 28) // PD_14: MAX2831 chip select
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| (0 << 29) // PD_15: MAX2831 RXHP control RXHP low = 100 Hz HPF
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| (1 << 30) // PD_16: MAX5865 chip select
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| (1 << 25) // PD_11: RFFC5072 Lock Detect
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| boot_bit(trigger_in, 0) // PD_12: TRIGGER IN
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.data = boot_bit(max283x_select, 1) // PD_14: !MAX2831 chip select
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| boot_bit(max2831_rxhp, 0) // PD_15: MAX2831 RXHP control RXHP low = 100 Hz HPF
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| (1 << 30) // PD_16: MAX5865 chip select
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| (1 << 25) // PD_11: RFFC5072 Lock Detect
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| boot_bit(trigger_in, 0) // PD_12: TRIGGER IN
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,
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.dir = (1 << 28) // PD_14: MAX2831 chip select
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| (1 << 29) // PD_15: MAX2831 RXHP control
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| (1 << 30) // PD_16: MAX5865 chip select
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| (0 << 25) // PD_11: RFFC5072 Lock Detect
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| boot_bit(trigger_in, 0) // PD_12: TRIGGER IN
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.dir = boot_bit(max283x_select, 1) // PD_14: !MAX2831 chip select
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| boot_bit(max2831_rxhp, 1) // PD_15: MAX2831 RXHP control
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| (1 << 30) // PD_16: MAX5865 chip select
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| (0 << 25) // PD_11: RFFC5072 Lock Detect
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| boot_bit(trigger_in, 0) // PD_12: TRIGGER IN
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#else
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.data = 0,
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.dir = 0
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||||
@@ -409,17 +408,17 @@ const PALConfig pal_default_config = {
|
||||
{
|
||||
// GPIO7
|
||||
#ifdef PRALINE
|
||||
.data = (0 << 0) // PE_0: Output
|
||||
| (0 << 1) // PE_1: MAX2831 !SHDN
|
||||
| (0 << 2) // PE_2: MAX2831 RXTX
|
||||
| boot_bit(p2_ctrl0, 0) // PE_3: P2_ctrl0
|
||||
| boot_bit(p2_ctrl1, 0) // PE_4: P2_ctrl1
|
||||
.data = (0 << 0) // PE_0: Output
|
||||
| boot_bit(max283x_enable, 0) // PE_1: MAX2831 !SHDN
|
||||
| boot_bit(max2831_rxtx_enable, 0) // PE_2: MAX2831 RXTX
|
||||
| boot_bit(p2_ctrl0, 0) // PE_3: P2_ctrl0
|
||||
| boot_bit(p2_ctrl1, 0) // PE_4: P2_ctrl1
|
||||
,
|
||||
.dir = (1 << 0) // PE_0: Output
|
||||
| (1 << 1) // PE_1: MAX2831 !SHDN
|
||||
| (1 << 2) // PE_2: MAX2831 RXTX
|
||||
| boot_bit(p2_ctrl0, 1) // PE_3: P2_ctrl0
|
||||
| boot_bit(p2_ctrl1, 1) // PE_4: P2_ctrl1
|
||||
.dir = (1 << 0) // PE_0: Output
|
||||
| boot_bit(max283x_enable, 1) // PE_1: MAX2831 !SHDN
|
||||
| boot_bit(max2831_rxtx_enable, 1) // PE_2: MAX2831 RXTX
|
||||
| boot_bit(p2_ctrl0, 1) // PE_3: P2_ctrl0
|
||||
| boot_bit(p2_ctrl1, 1) // PE_4: P2_ctrl1
|
||||
#else
|
||||
.data = 0,
|
||||
.dir = 0
|
||||
@@ -494,7 +493,7 @@ const PALConfig pal_default_config = {
|
||||
{map_sgpio_12.scu_port, map_sgpio_12.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_12.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO12: HOST_INVERT(I)
|
||||
#ifdef PRALINE
|
||||
|
||||
{6, 4, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // P6_4: SCT_CLK IN (Fast clock input, Mode 1)
|
||||
{map_sct_clk_in.scu_port, map_sct_clk_in.scu_pin, scu_config_normal_drive_t{.mode = map_sct_clk_in.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // P6_4: SCT_CLK IN (Fast clock input, Mode 1)
|
||||
{4, 10, scu_config_normal_drive_t{.mode = 7, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P4_10: FPGA Config Done (Input GND)
|
||||
{map_trigger_in.scu_port, map_trigger_in.scu_pin, scu_config_normal_drive_t{.mode = map_trigger_in.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_12: TRIGGER IN (Input GND, Mode 4)
|
||||
{map_trigger_out.scu_port, map_trigger_out.scu_pin, scu_config_normal_drive_t{.mode = map_trigger_out.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P2_6: TRIGGER
|
||||
@@ -504,10 +503,7 @@ const PALConfig pal_default_config = {
|
||||
|
||||
{4, 9, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO14/BANK2F3M4: CPLD_P81
|
||||
{4, 10, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO15/BANK2F3M6: CPLD_P78
|
||||
{2, 6, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 1}}, // MIXER_SCLK/P31: 33pF, RFFC5072.SCLK(I)
|
||||
{4, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // RXENABLE
|
||||
{4, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // XCVR_EN: 10K PD
|
||||
{1, 20, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_20 CS_XCVR: MAX2837.CS(I)
|
||||
{map_hpf.scu_port, map_hpf.scu_pin, scu_config_normal_drive_t{.mode = map_hpf.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_0 HPF
|
||||
{map_rx_amp.scu_port, map_rx_amp.scu_pin, scu_config_normal_drive_t{.mode = map_rx_amp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_11 RX_AMP
|
||||
{map_rx_amp_pwr.scu_port, map_rx_amp_pwr.scu_pin, scu_config_normal_drive_t{.mode = map_rx_amp_pwr.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_12 !RX_AMP_PWR
|
||||
@@ -515,43 +511,44 @@ const PALConfig pal_default_config = {
|
||||
#endif
|
||||
|
||||
// RADIO & RF PATH (MAX2831, RFFC5072, Mixers, Switches, Amps)
|
||||
{1, 3, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P1_3 SSP1_MISO: MAX2837.DOUT(O)
|
||||
{1, 4, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_4 SSP1_MOSI: MAX2837.DIN(I)
|
||||
{1, 19, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // P1_19 SSP1_SCK: MAX2837.SCLK(I)
|
||||
{map_lpf.scu_port, map_lpf.scu_pin, scu_config_normal_drive_t{.mode = map_lpf.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_1 LPF
|
||||
{1, 3, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P1_3 SSP1_MISO: MAX2837.DOUT(O)
|
||||
{1, 4, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_4 SSP1_MOSI: MAX2837.DIN(I)
|
||||
{1, 19, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // P1_19 SSP1_SCK: MAX2837.SCLK(I)
|
||||
{map_lpf.scu_port, map_lpf.scu_pin, scu_config_normal_drive_t{.mode = map_lpf.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_1 LPF
|
||||
{map_rffc5072_clock.scu_port, map_rffc5072_clock.scu_pin, scu_config_normal_drive_t{.mode = map_rffc5072_clock.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 1}}, // P2_6: MIXER_SCLK/P31: 33pF, RFFC5072.SCLK(I) PRALINE: P9_5: RFFC5072 SCLK
|
||||
{map_max283x_select.scu_port, map_max283x_select.scu_pin, scu_config_normal_drive_t{.mode = map_max283x_select.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P1_20 CS_XCVR: MAX2837.CS(I), PRALINE: PD_14: MAX2831 CS
|
||||
{map_max283x_enable.scu_port, map_max283x_enable.scu_pin, scu_config_normal_drive_t{.mode = map_max283x_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P4_6 max283x enable, PRALINE: PE_1: MAX2831 !SHDN
|
||||
|
||||
#ifdef PRALINE
|
||||
{5, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_4: RFFC ENX
|
||||
{5, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_5: RFFC RESETX
|
||||
{9, 5, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // P9_5: RFFC5072 SCLK
|
||||
{9, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 1, .ezi = 1, .zif = 0}}, // P9_2: RFFC5072 DATA (Bidirectional)
|
||||
{13, 11, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_11: RFFC Lock Detect
|
||||
{13, 14, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_14: MAX2831 CS
|
||||
{13, 15, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PD_15: MAX2831 RXHP
|
||||
{13, 16, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_16: MAX5864 CS
|
||||
{14, 1, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PE_1: MAX2831 !SHDN
|
||||
{14, 2, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PE_2: MAX2831 RXTX
|
||||
{map_p1_ctrl1.scu_port, map_p1_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl1.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 P1_CTRL1 (Output GND, Mode 4)
|
||||
{map_aa_en.scu_port, map_aa_en.scu_pin, scu_config_normal_drive_t{.mode = map_aa_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 0}}, // P1_14: AA_EN
|
||||
{map_rf5072_mix_en.scu_port, map_rf5072_mix_en.scu_pin, scu_config_normal_drive_t{.mode = map_rf5072_mix_en.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_0: RF5072 MIX EN
|
||||
{9, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_6: MAX2831 LD Input
|
||||
{map_tx_enable.scu_port, map_tx_enable.scu_pin, scu_config_normal_drive_t{.mode = map_tx_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_5: TX enable
|
||||
{10, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_1: LPF enable
|
||||
{10, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_2: RF amp enable
|
||||
{map_mix_bypass.scu_port, map_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_mix_bypass.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_3: MIX_ENABLE_N
|
||||
{map_rf_amp_enable.scu_port, map_rf_amp_enable.scu_pin, scu_config_normal_drive_t{.mode = map_rf_amp_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PA_2 RF_AMP_EN
|
||||
{13, 11, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_11: RFFC Lock Detect
|
||||
{map_max2831_rxhp.scu_port, map_max2831_rxhp.scu_pin, scu_config_normal_drive_t{.mode = map_max2831_rxhp.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PD_15: MAX2831 RXHP
|
||||
{13, 16, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_16: MAX5864 CS
|
||||
{map_max2831_rxtx_enable.scu_port, map_max2831_rxtx_enable.scu_pin, scu_config_normal_drive_t{.mode = map_max2831_rxtx_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PE_2: MAX2831 RXTX
|
||||
{map_p1_ctrl1.scu_port, map_p1_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl1.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 P1_CTRL1 (Output GND, Mode 4)
|
||||
{map_aa_en.scu_port, map_aa_en.scu_pin, scu_config_normal_drive_t{.mode = map_aa_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 0}}, // P1_14: AA_EN
|
||||
{map_rf5072_mix_en.scu_port, map_rf5072_mix_en.scu_pin, scu_config_normal_drive_t{.mode = map_rf5072_mix_en.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_0: RF5072 MIX EN
|
||||
{9, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_6: MAX2831 LD Input
|
||||
{map_tx_enable.scu_port, map_tx_enable.scu_pin, scu_config_normal_drive_t{.mode = map_tx_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_5: TX enable
|
||||
{10, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_1: LPF enable
|
||||
{10, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_2: RF amp enable
|
||||
{map_mix_bypass.scu_port, map_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_mix_bypass.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_3: MIX_ENABLE_N
|
||||
{map_rf_amp_enable.scu_port, map_rf_amp_enable.scu_pin, scu_config_normal_drive_t{.mode = map_rf_amp_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PA_2 RF_AMP_EN
|
||||
#else
|
||||
{map_rx_mix_bp.scu_port, map_rx_mix_bp.scu_pin, scu_config_normal_drive_t{.mode = map_rx_mix_bp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_3 RX_MIX_BP
|
||||
{5, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_ENX
|
||||
{map_tx_amp.scu_port, map_tx_amp.scu_pin, scu_config_normal_drive_t{.mode = map_tx_amp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_6 TX_AMP
|
||||
{5, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_7 CS_AD, PRALINE: RFFC5072 CS
|
||||
{5, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_RESETX
|
||||
{6, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // MIXER_SDATA
|
||||
{map_rx_mix_bp.scu_port, map_rx_mix_bp.scu_pin, scu_config_normal_drive_t{.mode = map_rx_mix_bp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_3 RX_MIX_BP
|
||||
|
||||
{map_tx_amp.scu_port, map_tx_amp.scu_pin, scu_config_normal_drive_t{.mode = map_tx_amp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_6 TX_AMP
|
||||
{5, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_7 CS_AD, PRALINE: RFFC5072 CS
|
||||
|
||||
{map_tx_mix_bypass.scu_port, map_tx_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_tx_mix_bypass.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 !TX MIX BYPASS
|
||||
{map_amp_bypass.scu_port, map_amp_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_amp_bypass.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_10 AMP_BYPASS
|
||||
{map_tx_amp_pwr.scu_port, map_tx_amp_pwr.scu_pin, scu_config_normal_drive_t{.mode = map_tx_amp_pwr.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // !TX_AMP_PWR
|
||||
{map_rx_mix_bypass.scu_port, map_rx_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_rx_mix_bypass.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_8 RX MIX BYPASS
|
||||
#endif
|
||||
|
||||
{map_rffc5072_select.scu_port, map_rffc5072_select.scu_pin, scu_config_normal_drive_t{.mode = map_rffc5072_select.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_4: MIXER_ENX
|
||||
{map_rffc5072_resetx.scu_port, map_rffc5072_resetx.scu_pin, scu_config_normal_drive_t{.mode = map_rffc5072_resetx.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_RESETX
|
||||
{map_rffc5072_sdata.scu_port, map_rffc5072_sdata.scu_pin, scu_config_normal_drive_t{.mode = map_rffc5072_sdata.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 1, .zif = 0}}, // P6_4: RFFC5072 DATA (Bidirectional) PRALINE P9_2
|
||||
|
||||
// SAFE TERMINATION (Unused pins grounded to prevent noise & save power)
|
||||
|
||||
#ifdef PRALINE
|
||||
@@ -584,7 +581,7 @@ const PALConfig pal_default_config = {
|
||||
{map_isp.scu_port, map_isp.scu_pin, scu_config_normal_drive_t{.mode = map_isp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_7: ISP: 10K PU, Unused
|
||||
{map_dfu_boot_0.scu_port, map_dfu_boot_0.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_boot_0.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_1: 10K PU, BOOT0
|
||||
{map_dfu_boot_1.scu_port, map_dfu_boot_1.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_boot_1.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_2: 10K PD, BOOT1
|
||||
{map_dfu_button.scu_port, map_dfu_button.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_button.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 1}}, // P2_8: BOOT2, DFU button
|
||||
{map_dfu_button.scu_port, map_dfu_button.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_button.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 1}}, // P2_8: 10K PD, BOOT2, DFU button
|
||||
{map_lcd_wrx.scu_port, map_lcd_wrx.scu_pin, scu_config_normal_drive_t{.mode = map_lcd_wrx.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
|
||||
|
||||
}};
|
||||
|
||||
Reference in New Issue
Block a user