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Gpio modify v4 (#3266)
* Refactor GPIO handling for RFFC5072: update pin mappings and simplify initialization * Refactor GPIO handling: replace portapack::gpio_dfu with dfu_button and clean up unused GPIOs * Refactor MAX283x GPIO handling: update pin mappings and simplify initialization * Refactor GPIO handling: update MAX2831 shutdown pin configuration * Refactor GPIO handling: add MAX2831 RXHP and RXTX control, update related configurations * Refactor MAX2831 frequency setting to include reference divider parameter and improve validation checks * Refactor MAX2831 frequency setting to remove reference divider parameter and improve frequency validation * copilot
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@@ -76,8 +76,8 @@ static constexpr uint32_t ssp_scr(
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/* MAX2831 uses 9-bit SPI transfers */
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static constexpr SPIConfig ssp_config_max283x = {
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.end_cb = NULL,
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.ssport = gpio_max283x_select.port(),
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.sspad = gpio_max283x_select.pad(),
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.ssport = map_max283x_select.gpio_port,
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.sspad = map_max283x_select.gpio_pad,
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.cr0 =
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CR0_CLOCKRATE(ssp_scr(ssp1_pclk_f, ssp1_cpsr, max283x_spi_f) + 3) | CR0_FRFSPI | CR0_DSS9BIT,
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.cpsr = ssp1_cpsr,
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@@ -95,8 +95,8 @@ void set_rx_buff_vcm(const size_t v) {
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/* MAX2837/MAX2839 use 16-bit SPI transfers */
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static constexpr SPIConfig ssp_config_max283x = {
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.end_cb = NULL,
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.ssport = gpio_max283x_select.port(),
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.sspad = gpio_max283x_select.pad(),
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.ssport = map_max283x_select.gpio_port,
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.sspad = map_max283x_select.gpio_pad,
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.cr0 =
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CR0_CLOCKRATE(ssp_scr(ssp1_pclk_f, ssp1_cpsr, max283x_spi_f) + 3) | CR0_FRFSPI | CR0_DSS16BIT,
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.cpsr = ssp1_cpsr,
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