From 7c715ed91303bf5561097e5b5597c5102996b19c Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Wed, 31 May 2017 15:21:25 -0700 Subject: [PATCH] CPLD: HDL for 20170522 hardware variant. --- .../cpld/20170522/portapack_h1_cpld.qpf | 30 ++ .../cpld/20170522/portapack_h1_cpld.qsf | 291 ++++++++++++++++++ .../cpld/20170522/portapack_h1_cpld.sdc | 116 +++++++ hardware/portapack_h1/cpld/20170522/top.vhd | 173 +++++++++++ 4 files changed, 610 insertions(+) create mode 100644 hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qpf create mode 100644 hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qsf create mode 100644 hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.sdc create mode 100644 hardware/portapack_h1/cpld/20170522/top.vhd diff --git a/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qpf b/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qpf new file mode 100644 index 000000000..0ced0c844 --- /dev/null +++ b/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 21:24:55 April 29, 2014 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.1" +DATE = "21:24:55 April 29, 2014" + +# Revisions + +PROJECT_REVISION = "portapack_h1_cpld" diff --git a/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qsf b/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qsf new file mode 100644 index 000000000..c2a274d8a --- /dev/null +++ b/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qsf @@ -0,0 +1,291 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2014 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition +# Date created = 21:24:55 April 29, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# portapack_h1_cpld_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX V" +set_global_assignment -name DEVICE 5M40ZE64C5 +set_global_assignment -name TOP_LEVEL_ENTITY top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:24:55 APRIL 29, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 64 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/modelsim -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name SDC_FILE portapack_h1_cpld.sdc +set_global_assignment -name VHDL_FILE top.vhd +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" +set_location_assignment PIN_43 -to LCD_DB[15] +set_location_assignment PIN_44 -to LCD_DB[14] +set_location_assignment PIN_45 -to LCD_DB[13] +set_location_assignment PIN_46 -to LCD_DB[12] +set_location_assignment PIN_47 -to LCD_DB[11] +set_location_assignment PIN_48 -to LCD_DB[10] +set_location_assignment PIN_49 -to LCD_DB[9] +set_location_assignment PIN_50 -to LCD_DB[8] +set_location_assignment PIN_51 -to LCD_DB[7] +set_location_assignment PIN_52 -to LCD_DB[6] +set_location_assignment PIN_53 -to LCD_DB[5] +set_location_assignment PIN_54 -to LCD_DB[4] +set_location_assignment PIN_55 -to LCD_DB[3] +set_location_assignment PIN_56 -to LCD_DB[2] +set_location_assignment PIN_58 -to LCD_DB[1] +set_location_assignment PIN_59 -to LCD_DB[0] +set_location_assignment PIN_60 -to LCD_RDX +set_location_assignment PIN_62 -to LCD_RS +set_location_assignment PIN_63 -to LCD_TE +set_location_assignment PIN_61 -to LCD_WRX +set_location_assignment PIN_10 -to SW_D +set_location_assignment PIN_28 -to SW_L +set_location_assignment PIN_9 -to SW_R +set_location_assignment PIN_11 -to SW_ROT_A +set_location_assignment PIN_12 -to SW_ROT_B +set_location_assignment PIN_13 -to SW_SEL +set_location_assignment PIN_25 -to SW_U +set_location_assignment PIN_1 -to TP_D +set_location_assignment PIN_2 -to TP_L +set_location_assignment PIN_64 -to TP_R +set_location_assignment PIN_3 -to TP_U +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_D +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_L +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_R +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_A +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_ROT_B +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_SEL +set_instance_assignment -name IO_STANDARD "3.3V SCHMITT TRIGGER INPUT" -to SW_U +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_D +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_L +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_R +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TP_U +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_DB[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RDX +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RS +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_TE +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_WRX +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH top_tb -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME top_tb -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME uut -section_id top_tb +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME top_tb -section_id top_tb +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "500 ns" -section_id top_tb +set_global_assignment -name EDA_TEST_BENCH_FILE top_tb.vhd -section_id top_tb +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)" +set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR /home/jboone/src/portapack/portapack_hackrf/hardware/portapack_h1/cpld -section_id eda_board_design_boundary_scan +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan +set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_NCE_PIN OFF +set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name GENERATE_RBF_FILE OFF +set_global_assignment -name GENERATE_SVF_FILE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH BUS-HOLD" +set_location_assignment PIN_38 -to LCD_RESETX +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_RESETX +set_location_assignment PIN_18 -to MCU_D[7] +set_location_assignment PIN_19 -to MCU_D[6] +set_location_assignment PIN_21 -to MCU_D[5] +set_location_assignment PIN_20 -to MCU_D[4] +set_location_assignment PIN_22 -to MCU_D[3] +set_location_assignment PIN_24 -to MCU_D[2] +set_location_assignment PIN_27 -to MCU_D[1] +set_location_assignment PIN_26 -to MCU_D[0] +set_location_assignment PIN_33 -to MCU_ADDR +set_location_assignment PIN_42 -to MCU_DIR +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_ADDR +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_DIR +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_D +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_L +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_R +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_U +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_B +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_SEL +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SW_ROT_A +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_DB[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RDX +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RESETX +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_RS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_TE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_WRX +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_ADDR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_D[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_L +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_R +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_A +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_ROT_B +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SW_U +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_L +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_R +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to TP_U +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[15] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[14] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[13] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[12] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[11] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[10] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[9] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[8] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[7] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[6] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[5] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[4] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[3] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[2] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[1] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_DB[0] +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RDX +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RESETX +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_RS +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_TE +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_WRX +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_ADDR +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[7] +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[6] +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[5] +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[4] +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[3] +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[2] +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[1] +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_D[0] +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_DIR +set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_D +set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_L +set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_R +set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_A +set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_ROT_B +set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_SEL +set_instance_assignment -name SLOW_SLEW_RATE ON -to SW_U +set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_D +set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_L +set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_R +set_instance_assignment -name SLOW_SLEW_RATE ON -to TP_U +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name IOBANK_VCCIO 1.8V -section_id 2 +set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1 +set_instance_assignment -name PCI_IO OFF -to MCU_DIR +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER ON +set_location_assignment PIN_37 -to LCD_BACKLIGHT +set_instance_assignment -name IO_STANDARD "1.8 V" -to LCD_BACKLIGHT +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to LCD_BACKLIGHT +set_instance_assignment -name SLOW_SLEW_RATE ON -to LCD_BACKLIGHT +set_location_assignment PIN_4 -to AUDIO_RESETX +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_RESETX +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AUDIO_RESETX +set_instance_assignment -name SLOW_SLEW_RATE ON -to AUDIO_RESETX +set_location_assignment PIN_30 -to MCU_LCD_RD +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_RD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_RD +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_RD +set_location_assignment PIN_40 -to MCU_LCD_WR +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_WR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_WR +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_WR +set_instance_assignment -name PCI_IO OFF -to MCU_LCD_WR +set_location_assignment PIN_32 -to MCU_IO_STBX +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_IO_STBX +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_IO_STBX +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_IO_STBX +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_R +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_D +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_L +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TP_U +set_location_assignment PIN_31 -to MCU_LCD_TE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_LCD_TE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_LCD_TE +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_LCD_TE +set_location_assignment PIN_34 -to MCU_P2_8 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MCU_P2_8 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MCU_P2_8 +set_instance_assignment -name SLOW_SLEW_RATE ON -to MCU_P2_8 +set_instance_assignment -name PCI_IO OFF -to MCU_P2_8 \ No newline at end of file diff --git a/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.sdc b/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.sdc new file mode 100644 index 000000000..7417b9444 --- /dev/null +++ b/hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.sdc @@ -0,0 +1,116 @@ +## Generated SDC file "portapack_hackrf_one_cpld.sdc" + +## Copyright (C) 1991-2014 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" + +## DATE "Sat May 3 10:22:18 2014" + +## +## DEVICE "5M40ZE64C5" +## + +# RS = 0, D = DB[15:8] +# wait max(tast = 0 ns, CPLD setup = ?) +# WR = 0, D = DB[7:0] +# wait max(CPLD ) + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + +set mcu_clk_period 4.9 + +set lcd_data_wr_setup 10.0 +set lcd_data_wr_hold 10.0 + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {MCU_LCD_WR} -period 66.000 -waveform { 0.000 33.000 } [get_ports {MCU_LCD_WR}] +#create_clock -name strobe_virt -period 66.000 + +#************************************************************** +# Create Generated Clock +#************************************************************** + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + + + +#************************************************************** +# Set Input Delay +#************************************************************** + +#set_input_delay -clock strobe_virt [get_ports {D[*]}] + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +#set_false_path -from [get_clocks {MCU_IO_STBX}] -to [get_ports {TP_D TP_L TP_R TP_U}] +#set_false_path -from [get_ports {SW_D SW_L SW_R SW_ROT_A SW_ROT_B SW_SEL SW_U}] -to [get_ports {MCU_D[*]}] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + diff --git a/hardware/portapack_h1/cpld/20170522/top.vhd b/hardware/portapack_h1/cpld/20170522/top.vhd new file mode 100644 index 000000000..d9969ff46 --- /dev/null +++ b/hardware/portapack_h1/cpld/20170522/top.vhd @@ -0,0 +1,173 @@ +-- +-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc. +-- +-- This file is part of PortaPack. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2, or (at your option) +-- any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; see the file COPYING. If not, write to +-- the Free Software Foundation, Inc., 51 Franklin Street, +-- Boston, MA 02110-1301, USA. + +library ieee; +use ieee.std_logic_1164.all; + +entity top is + port ( + MCU_D : inout std_logic_vector(7 downto 0); + MCU_DIR : in std_logic; + MCU_IO_STBX : in std_logic; + MCU_LCD_WR : in std_logic; + MCU_ADDR : in std_logic; + MCU_LCD_TE : out std_logic; + MCU_P2_8 : in std_logic; + MCU_LCD_RD : in std_logic; + + TP_U : out std_logic; + TP_D : out std_logic; + TP_L : out std_logic; + TP_R : out std_logic; + + SW_SEL : in std_logic; + SW_ROT_A : in std_logic; + SW_ROT_B : in std_logic; + SW_U : in std_logic; + SW_D : in std_logic; + SW_L : in std_logic; + SW_R : in std_logic; + + LCD_RESETX : out std_logic; + LCD_RS : out std_logic; + LCD_WRX : out std_logic; + LCD_RDX : out std_logic; + LCD_DB : inout std_logic_vector(15 downto 0); + LCD_TE : in std_logic; + LCD_BACKLIGHT : out std_logic; + + AUDIO_RESETX : out std_logic + ); +end top; + +architecture rtl of top is + + signal switches : std_logic_vector(7 downto 0); + + type data_direction_t is (from_mcu, to_mcu); + signal data_dir : data_direction_t; + + signal mcu_data_out_lcd : std_logic_vector(7 downto 0); + signal mcu_data_out_io : std_logic_vector(7 downto 0); + signal mcu_data_out : std_logic_vector(7 downto 0); + signal mcu_data_in : std_logic_vector(7 downto 0); + + signal lcd_data_in : std_logic_vector(15 downto 0); + signal lcd_data_in_mux : std_logic_vector(7 downto 0); + signal lcd_data_out : std_logic_vector(15 downto 0); + + signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0'); + signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0'); + + signal tp_q : std_logic_vector(7 downto 0) := (others => '0'); + + signal lcd_reset_q : std_logic := '1'; + signal lcd_backlight_q : std_logic := '0'; + + signal audio_reset_q : std_logic := '1'; + + signal dir_read : boolean; + signal dir_write : boolean; + + signal lcd_read_strobe : boolean; + signal lcd_write_strobe : boolean; + signal lcd_write : boolean; + + signal io_strobe : boolean; + signal io_read_strobe : boolean; + signal io_write_strobe : boolean; + +begin + + -- I/O data + switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R; + + TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z'; + TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z'; + TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z'; + TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z'; + + LCD_BACKLIGHT <= lcd_backlight_q; + + MCU_LCD_TE <= LCD_TE; + + -- State management + data_dir <= to_mcu when MCU_DIR = '1' else from_mcu; + dir_read <= (data_dir = to_mcu); + dir_write <= (data_dir = from_mcu); + + io_strobe <= (MCU_IO_STBX = '0'); + io_read_strobe <= io_strobe and dir_read; + + lcd_read_strobe <= (MCU_LCD_RD = '1'); + lcd_write <= not lcd_read_strobe; + + -- LCD interface + LCD_RS <= MCU_ADDR; + LCD_RDX <= not MCU_LCD_RD; + LCD_WRX <= not MCU_LCD_WR; + + lcd_data_out <= lcd_data_out_q & mcu_data_in; + lcd_data_in <= LCD_DB; + LCD_DB <= lcd_data_out when lcd_write else (others => 'Z'); + + LCD_RESETX <= not lcd_reset_q; + AUDIO_RESETX <= not audio_reset_q; + + -- MCU interface + mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q; + mcu_data_out_io <= switches; + mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd; + + mcu_data_in <= MCU_D; + MCU_D <= mcu_data_out when dir_read else (others => 'Z'); + + -- Synchronous behaviors: + -- LCD write: Capture LCD high byte on LCD_WRX falling edge. + process(MCU_LCD_WR, mcu_data_in) + begin + if rising_edge(MCU_LCD_WR) then + lcd_data_out_q <= mcu_data_in; + end if; + end process; + + -- LCD read: Capture LCD low byte on LCD_RD falling edge. + process(MCU_LCD_RD, lcd_data_in) + begin + if falling_edge(MCU_LCD_RD) then + lcd_data_in_q <= lcd_data_in(7 downto 0); + end if; + end process; + + -- I/O write (to resistive touch panel): Capture data from + -- MCU and hold on TP pins until further notice. + process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR) + begin + if rising_edge(MCU_IO_STBX) and dir_write then + if MCU_ADDR = '0' then + tp_q <= mcu_data_in; + else + lcd_reset_q <= mcu_data_in(0); + audio_reset_q <= mcu_data_in(1); + lcd_backlight_q <= mcu_data_in(7); + end if; + end if; + end process; +end rtl;