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Added carrier wake up in Xylos TX and cute icons

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This commit is contained in:
furrtek
2016-05-27 06:48:04 +02:00
parent 7a90eab407
commit 6a0816ba56
31 changed files with 636 additions and 285 deletions
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firmware/baseband-tx/proc_xylos.cpp
+44 -30
View File
@@ -42,47 +42,61 @@ void XylosProcessor::execute(const buffer_c8_t& buffer) {
if (s >= 9) {
s = 0;
if (sample_count >= CCIR_TONELENGTH) {
if (shared_memory.transmit_done == false) {
message.n = byte_pos; // Inform UI about progress (just as eye candy)
shared_memory.application_queue.push(message);
digit = shared_memory.xylosdata[byte_pos++];
if (silence) {
if (sample_count >= SILENCE) {
silence = false;
sample_count = CCIR_TONELENGTH;
} else {
sample_count++;
}
} else {
if (sample_count >= CCIR_TONELENGTH) {
if (shared_memory.transmit_done == false) {
message.n = byte_pos; // Inform UI about progress (just as eye candy)
shared_memory.application_queue.push(message);
digit = shared_memory.xylosdata[byte_pos++];
}
if (digit == 0xFF) {
message.n = 25; // End of message code
shared_memory.transmit_done = true;
shared_memory.application_queue.push(message);
}
if (digit == 0xFF) {
message.n = 25; // End of message code
shared_memory.transmit_done = true;
shared_memory.application_queue.push(message);
sample_count = 0;
} else {
sample_count++;
}
sample_count = 0;
} else {
sample_count++;
aphase += ccir_phases[digit];
}
aphase += ccir_phases[digit];
} else {
s++;
}
sample = (sine_table_f32[(aphase & 0x03FF0000)>>18]*255);
// Audio preview sample generation: 1536000/48000 = 32
/*if (as >= 31) {
as = 0;
audio[ai++] = sample * 128;
if (silence) {
re = 0;
im = 0;
} else {
as++;
}*/
//FM
frq = sample * 1000; // ~25kHz wide
phase = (phase + frq);
sphase = phase + (256<<16);
sample = (sine_table_f32[(aphase & 0x03FF0000)>>18]*255);
// Audio preview sample generation: 1536000/48000 = 32
/*if (as >= 31) {
as = 0;
audio[ai++] = sample * 128;
} else {
as++;
}*/
//FM
frq = sample * 500; // To check !
phase = (phase + frq);
sphase = phase + (256<<16);
re = (sine_table_f32[(sphase & 0x03FF0000)>>18]*127);
im = (sine_table_f32[(phase & 0x03FF0000)>>18]*127);
re = (sine_table_f32[(sphase & 0x03FF0000)>>18]*127);
im = (sine_table_f32[(phase & 0x03FF0000)>>18]*127);
}
buffer.p[i] = {(int8_t)re,(int8_t)im};
}
firmware/baseband-tx/proc_xylos.hpp
+4 -2
View File
@@ -31,8 +31,9 @@
#include "audio_output.hpp"
#include "baseband_processor.hpp"
#define CCIR_TONELENGTH 15360-1 // 1536000/10/10
#define PHASEV 436.91 // (65536*1024)/1536000*10
#define CCIR_TONELENGTH 15360-1 // 1536000/10/10
#define PHASEV 436.91 // (65536*1024)/1536000*10
#define SILENCE 61440-1 // 400ms
class XylosProcessor : public BasebandProcessor {
public:
@@ -73,6 +74,7 @@ private:
uint32_t sample_count = CCIR_TONELENGTH;
uint32_t aphase, phase, sphase;
int32_t sample, frq;
bool silence = true;
TXDoneMessage message;
//AudioOutput audio_output;