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Resolved root cause for loss of bluetooth functionality and added more testing options (#3049)

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* Added PRO button to analog_audio.cpp for debugging metallic ringing sounds in Audio app. Ensured consitency to 4MHz in analog_audio.cpp

* Restored blutooth after loss.

* Added several sampling rates to analog_audio for testing.

* Ran format-code.sh

* Fixed 0x03 mode for DC/Q-INV/Q-SHFT being set at every tuning and sample rate change. This was the root cause for loss of bluetooth before. Sample rate, and frequency can now be changed without need for manually resetting DC/Q-INV/Q-SHIFT settings. Updated method for setting frequncies in praline so that we have more testing options.

* Ran format-code.sh and cleaned up stale comments.

* Addressed comments, and removed commented line, opting for higher register values, 5E and 5D. Added WFM Debug View to support testing demodulation ringing.

* Addressed comments in PR conversation to clean comments and ensure consistency at initializtion accross updated methods and displays.

* Ran format-code.sh
This commit is contained in:
stafur
2026-02-26 11:16:07 -05:00
committed by GitHub
parent cd7c412aa4
commit 56adca3bf6
7 changed files with 280 additions and 17 deletions
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firmware/application/radio.cpp
+17 -11
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@@ -154,11 +154,26 @@ void init() {
baseband_codec.init();
#ifdef PRALINE
/* Praline-Specific Bus and Gateware Configuration */
// SYNC SGPIO TO FPGA CLOCK:
// Configure all 16 SGPIO slices to use the external clock (SGPIO8)
// provided by the FPGA. This allows the MCU to stay at 40MHz
// while the data bus scales to the RF sample rate.
// Bit 2:1 of SGPIO_MUX_CFG = 01 (External clock from SGPIO8)
// SYNC SGPIO TO FPGA CLOCK WITH FALLING EDGE LATCH
for (int i = 0; i < 16; i++) {
// (1 << 1) = External clock from SGPIO8
// (1 << 3) = Sample on the FALLING edge of the clock
LPC_SGPIO->SGPIO_MUX_CFG[i] = (1 << 1) | (1 << 3);
}
/* Initialize FPGA registers - DC_BLOCK must be enabled for RX */
// debug::fpga::init();
// These FPGA registers control DC_BLOCK, Q-Inv, QUARTER SHIFT, and Decimation.
fpga_debug_register_write(1, 0x03); // DC_BLOCK=1, QUARTER_SHIFT=1, Q_INVERT=0
fpga_debug_register_write(2, 0x03); // RX_DECIM=8 (2^3 decimation for testing 20 MHz -> 2.5 MHz with audio for now)
fpga_debug_register_write(1, 0x01); // DC_BLOCK=1, QUARTER_SHIFT=0, Q_INVERT=0
fpga_debug_register_write(2, 0x00); // RX_DECIM=No Decim
fpga_debug_register_write(3, 0x00); // TX_CTRL=0
fpga_debug_register_write(4, 0x00); // TX_INTRP=0
fpga_debug_register_write(5, 0x00); // TX_PSTEP=0
@@ -210,10 +225,6 @@ void set_direction(const rf::Direction new_direction) {
#ifdef PRALINE
// This FPGA registers fix DC_BLOCK, Q-Inv, QUARTER SHIFT, and Decimation.
fpga_debug_register_write(1, 0x03); // DC_BLOCK, Q-Inv, no-QUARTER_SHIFT.
fpga_debug_register_write(2, 0x03); // RX_DECIM=8 (2^3 decimation for testing 20 MHz -> 2.5 MHz with audio for now)
// Q inversion controlled by GPIO0[13] (SGPIO12), not FPGA register
bool q_invert = mixer_invert ^ baseband_invert;
if (q_invert) {
@@ -284,11 +295,6 @@ bool set_tuning_frequency(const rf::Frequency frequency) {
mixer_invert = tuning_config.mixer_invert;
#ifdef PRALINE
// TEST: Force baseband invert for Praline (like r9)
// baseband_invert = (direction == rf::Direction::Receive);
// CORRECT: FPGA register 1 only controls DC_BLOCK
fpga_debug_register_write(1, 0x01); // DC_BLOCK only, no QUARTER_SHIFT!
// Q inversion controlled by GPIO0[13] (SGPIO12), not FPGA register
bool q_invert = mixer_invert ^ baseband_invert;