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Next praline clean up (#3077)

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* Cleaned up #ifndef PRALINE and updated logic to being with #ifdef PRALINE entries where possible to make logic flow for PRALINE code execution pipeline clearer. Cleaned up compiletime warnings for PRALINE related codebase updates.

* Addressed comments provided by copilot during PR review. Combed through frequency definitions for consistency between PLL A and PLL B register definitions for CLKs 0-7. Ensured CLK3/LK6 <- SMA PORTs and CLK7 <- not utiliized are disabled during core development phase to support root cause analysis of any spectral artifacts. Updated MCU frequency to 40MHz to ensure audio harmonics are outside FM radio band range (< 80 MHz, >120MHz) and added comments clarifying choice of 40 over 10 MHz for potential future root cause analysis in other bands where audio may be expected as needed. Added CLK6 and CLK7 to Clocks Status View Debug display. Moved CLK defintions and PLL instantiations for components that are most RF sensitive to PLL A. Left others in PLL B. That is move FPGA CLK1 to PLL B, while moving CLK2, CLK4, and CLK5 to PLL A.

* Cleaned up PLL A and B XTAL reference checks relative to 800 MHz.
This commit is contained in:
stafur
2026-03-07 19:39:53 -05:00
committed by GitHub
parent 561143cfb0
commit 52239d320a
10 changed files with 277 additions and 129 deletions
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firmware/common/baseband_sgpio.cpp
+8 -10
View File
@@ -199,22 +199,22 @@ constexpr uint32_t out_mux_cfg(const P_OUT_CFG out, const P_OE_CFG oe) {
constexpr uint32_t data_sgpio_mux_cfg(
const CONCAT_ENABLE concat_enable,
const CONCAT_ORDER concat_order) {
#ifndef PRALINE
return (1U << 0) | (0U << 1) | (0U << 3) | (3U << 5) | (1U << 7) | (0U << 9) | (toUType(concat_enable) << 11) | (toUType(concat_order) << 12);
#else
#ifdef PRALINE
return (1U << 0) | (0U << 1) | (3U << 3) | (3U << 5) | (1U << 7) | (0U << 9) | (toUType(concat_enable) << 11) | (toUType(concat_order) << 12);
// Bits 3-4: CLK_SOURCE_SLICE_MODE = 3 (slice D as clock source for data slices)
#else
return (1U << 0) | (0U << 1) | (0U << 3) | (3U << 5) | (1U << 7) | (0U << 9) | (toUType(concat_enable) << 11) | (toUType(concat_order) << 12);
#endif
}
constexpr uint32_t data_slice_mux_cfg(
const PARALLEL_MODE parallel_mode,
const CLK_CAPTURE_MODE clk_capture_mode) {
#ifndef PRALINE
return (0U << 0) | (toUType(clk_capture_mode) << 1) | (1U << 2) | (0U << 3) | (0U << 4) | (toUType(parallel_mode) << 6) | (0U << 8);
#else
#ifdef PRALINE
return (0U << 0) | (toUType(clk_capture_mode) << 1) | (1U << 2) | (0U << 3) | (1U << 4) | (toUType(parallel_mode) << 6) | (0U << 8);
// Bit 4 CLKGEN_MODE: 0=internal counter, 1=external clock (REQUIRED for PRALINE!)
#else
return (0U << 0) | (toUType(clk_capture_mode) << 1) | (1U << 2) | (0U << 3) | (0U << 4) | (toUType(parallel_mode) << 6) | (0U << 8);
#endif
}
@@ -330,10 +330,6 @@ void SGPIO::configure(const Direction direction) {
const auto clk_capture_mode = data_clk_capture_mode(direction);
const auto single_slice = !slice_mode_multislice;
#ifndef PRALINE
uint32_t slice_enable_mask = 0;
#endif
#ifdef PRALINE
// Configure slice D as clock generator (REQUIRED for PRALINE!)
// Reference: HackRF sgpio.c line 193
@@ -347,6 +343,8 @@ void SGPIO::configure(const Direction direction) {
LPC_SGPIO->REG_SS[slice_d] = 0x11111111;
uint32_t slice_enable_mask = (1U << slice_d); // Start with slice D enabled
#else
uint32_t slice_enable_mask = 0;
#endif
for (size_t i = 0; i < slice_count; i++) {