Next praline clean up (#3077)

* Cleaned up #ifndef PRALINE and updated logic to being with #ifdef PRALINE entries where possible to make logic flow for PRALINE code execution pipeline clearer. Cleaned up compiletime warnings for PRALINE related codebase updates.

* Addressed comments provided by copilot during PR review. Combed through frequency definitions for consistency between PLL A and PLL B register definitions for CLKs 0-7. Ensured CLK3/LK6 <- SMA PORTs and CLK7 <- not utiliized are disabled during core development phase to support root cause analysis of any spectral artifacts. Updated MCU frequency to 40MHz to ensure audio harmonics are outside FM radio band range (< 80 MHz, >120MHz) and added comments clarifying choice of 40 over 10 MHz for potential future root cause analysis in other bands where audio may be expected as needed. Added CLK6 and CLK7 to Clocks Status View Debug display. Moved CLK defintions and PLL instantiations for components that are most RF sensitive to PLL A. Left others in PLL B. That is move FPGA CLK1 to PLL B, while moving CLK2, CLK4, and CLK5 to PLL A.

* Cleaned up PLL A and B XTAL reference checks relative to 800 MHz.

firmware/application/portapack.cpp

@@ -392,18 +392,8 @@ static void set_cpu_clock_speed() {
 #endif
 
     cgu::pll1::enable();
-#ifndef PRALINE
-    while (!cgu::pll1::is_locked());
 
-    set_clock_config(clock_config_pll1_step);
-    /* Delay >50us at 90-110MHz clock speed */
-    volatile uint32_t delay = 1400;
-    while (delay--);
-    set_clock_config(clock_config_pll1);
-
-    /* Remove /2P divider from PLL1 output to achieve full speed */
-    cgu::pll1::direct();
-#else
+#ifdef PRALINE
     // Wait for PLL1 to lock with timeout
     {
         uint32_t timeout = 100000;
@@ -423,6 +413,18 @@ static void set_cpu_clock_speed() {
         /* Remove /2P divider from PLL1 output to achieve full speed */
         cgu::pll1::direct();
     }
+#else
+    while (!cgu::pll1::is_locked());
+
+    set_clock_config(clock_config_pll1_step);
+    /* Delay >50us at 90-110MHz clock speed */
+    volatile uint32_t delay = 1400;
+    while (delay--);
+    set_clock_config(clock_config_pll1);
+
+    /* Remove /2P divider from PLL1 output to achieve full speed */
+    cgu::pll1::direct();
+
 #endif
 }
 
@@ -660,6 +662,7 @@ init_status_t init() {
         draw_splash_screen_icon(2, ui::bitmap_icon_sd);
 
     init_status_t return_code = init_status_t::INIT_SUCCESS;
+
 #ifndef PRALINE
     // HackRF One uses CPLD - load it via JTAG
     if (!hackrf::cpld::load_sram()) {