mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-08-17 21:24:02 +00:00
Next praline clean up (#3077)
* Cleaned up #ifndef PRALINE and updated logic to being with #ifdef PRALINE entries where possible to make logic flow for PRALINE code execution pipeline clearer. Cleaned up compiletime warnings for PRALINE related codebase updates. * Addressed comments provided by copilot during PR review. Combed through frequency definitions for consistency between PLL A and PLL B register definitions for CLKs 0-7. Ensured CLK3/LK6 <- SMA PORTs and CLK7 <- not utiliized are disabled during core development phase to support root cause analysis of any spectral artifacts. Updated MCU frequency to 40MHz to ensure audio harmonics are outside FM radio band range (< 80 MHz, >120MHz) and added comments clarifying choice of 40 over 10 MHz for potential future root cause analysis in other bands where audio may be expected as needed. Added CLK6 and CLK7 to Clocks Status View Debug display. Moved CLK defintions and PLL instantiations for components that are most RF sensitive to PLL A. Left others in PLL B. That is move FPGA CLK1 to PLL B, while moving CLK2, CLK4, and CLK5 to PLL A. * Cleaned up PLL A and B XTAL reference checks relative to 800 MHz.
This commit is contained in:
stafur
GitHub
@@ -35,14 +35,14 @@ using namespace lpc43xx;
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extern "C" {
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#include "fpga_bridge.h"
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}
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// Need access to ssp1_arbiter from radio namespace
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// Need access to ssp1_arbiter from radio namespace for FPGA related radio method dependencies.
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#include "radio.hpp"
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#endif
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constexpr uint32_t si5351_vco_f = 800000000;
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#ifdef PRALINE
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constexpr uint32_t si5351_vco_afe_f = 800000000; // Optimal for 3.072 MHz sample frequencies commonly used by apps
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constexpr uint32_t si5351_vco_afe_f = 800000000; // If necessary may be changed to 768 MHz for optimal for 3.072 MHz sample frequencies commonly used by apps
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#endif
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constexpr si5351::Inputs si5351_inputs{
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@@ -67,23 +67,43 @@ constexpr si5351::PLL si5351_pll_xtal_25m{
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.c = 1,
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};
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// PLL A registers (Base 26)
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constexpr auto si5351_pll_a_xtal_reg = si5351_pll_xtal_25m.reg(0);
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#ifdef PRALINE
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// Define pll_a from 25MHz clock for stable PLL A, and AFE locked reference
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// PLL A: 800 MHz VCO (32x Multiplier for jitter-free 3.072 MHz sampling)
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constexpr si5351::PLL si5351_pll_xtal_800m{
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.f_in = si5351_inputs.f_xtal,
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.a = 32,
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constexpr si5351::PLL si5351_pll_a_afe_800m{
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.f_in = si5351_inputs.f_xtal, // 25,000,000 Hz
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.a = 32, // Multiplier: 25 * 32 = 800
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.b = 0,
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.c = 1,
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};
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constexpr auto si5351_pll_a_800_reg = si5351_pll_xtal_800m.reg(0); // Base 26
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// PLL A: registers (Base 34) 800 MHz VCO (For jitter-free AFE sampling frequencies)
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constexpr auto si5351_pll_a_800_reg = si5351_pll_a_afe_800m.reg(0); // Base 26
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// PLL B: registers (Base 34) 800 MHz VCO (32x Multiplier for stable Digital/SGPIO bus)
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constexpr auto si5351_pll_b_800_reg = si5351_pll_xtal_25m.reg(1); // Base 34
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constexpr auto si5351_pll_b_xtal_reg = si5351_pll_xtal_25m.reg(1);
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static_assert(si5351_pll_a_afe_800m.f_vco() == si5351_vco_f, "PLL A XTAL frequency wrong");
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static_assert(si5351_pll_a_afe_800m.p1() == 3584, "PLL A XTAL P1 wrong");
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static_assert(si5351_pll_a_afe_800m.p2() == 0, "PLL A XTAL P2 wrong");
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static_assert(si5351_pll_a_afe_800m.p3() == 1, "PLL A XTAL P3 wrong");
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// Define pll_b 25MHz clock for stable PLL B
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// PLL B: 800 MHz VCO (32x Multiplier for (For stable Digital/SGPIO bus)
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constexpr si5351::PLL si5351_pll_b_800m{
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.f_in = si5351_inputs.f_xtal, // 25,000,000 Hz
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.a = 32, // Multiplier: 25 * 32 = 800
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.b = 0,
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.c = 1,
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};
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// PLL B: registers (Base 34) 800 MHz VCO (For stable Digital/SGPIO bus)
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constexpr auto si5351_pll_b_800_reg = si5351_pll_b_800m.reg(1); // Base 34
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static_assert(si5351_pll_b_800m.f_vco() == si5351_vco_f, "PLL B XTAL frequency wrong");
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static_assert(si5351_pll_b_800m.p1() == 3584, "PLL B XTAL P1 wrong");
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static_assert(si5351_pll_b_800m.p2() == 0, "PLL B XTAL P2 wrong");
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static_assert(si5351_pll_b_800m.p3() == 1, "PLL B XTAL P3 wrong");
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#else
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// PLL A registers (Base 26)
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constexpr auto si5351_pll_a_xtal_reg = si5351_pll_xtal_25m.reg(0);
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static_assert(si5351_pll_xtal_25m.f_vco() == si5351_vco_f, "PLL XTAL frequency wrong");
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static_assert(si5351_pll_xtal_25m.p1() == 3584, "PLL XTAL P1 wrong");
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static_assert(si5351_pll_xtal_25m.p2() == 0, "PLL XTAL P2 wrong");
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@@ -99,13 +119,6 @@ constexpr si5351::PLL si5351_pll_clkin_10m{
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constexpr auto si5351c_pll_b_clkin_reg = si5351_pll_clkin_10m.reg(1);
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constexpr auto si5351a_pll_a_clkin_reg = si5351_pll_clkin_10m.reg(0);
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#ifndef PRALINE
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static_assert(si5351_pll_xtal_25m.f_vco() == si5351_vco_f, "PLL XTAL frequency wrong");
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static_assert(si5351_pll_xtal_25m.p1() == 3584, "PLL XTAL P1 wrong");
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static_assert(si5351_pll_xtal_25m.p2() == 0, "PLL XTAL P2 wrong");
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static_assert(si5351_pll_xtal_25m.p3() == 1, "PLL XTAL P3 wrong");
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#endif
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static_assert(si5351_pll_clkin_10m.f_vco() == si5351_vco_f, "PLL CLKIN frequency wrong");
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static_assert(si5351_pll_clkin_10m.p1() == 9728, "PLL CLKIN P1 wrong");
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static_assert(si5351_pll_clkin_10m.p2() == 0, "PLL CLKIN P2 wrong");
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@@ -153,6 +166,26 @@ constexpr si5351::MultisynthFractional si5351_ms_afe_10m{
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.b = 0,
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.c = 1,
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.r_div = 0};
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// (20 MHz from 800 MHz VCO: 800 / 40 = 20)
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constexpr si5351::MultisynthFractional si5351_ms_afe_20m{
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.f_src = si5351_vco_afe_f,
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.a = 40,
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.b = 0,
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.c = 1,
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.r_div = 0,
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};
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// (25 MHz from 800 MHz VCO: 800 / 32 = 25)
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// Define xtal MultiSynth 25MHz clock for stable PLL A, and AFE locked XTAL reference
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constexpr si5351::MultisynthFractional si5351_ms_afe_25m{
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.f_src = si5351_vco_afe_f, // 800,000,000 Hz
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.a = 32, // 800 / 32 = 25 MHz
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.b = 0,
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.c = 1,
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.r_div = 0 // No final bit-shifting
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};
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// (40 MHz from 800 MHz VCO: 800 / 20 = 40)
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constexpr si5351::MultisynthFractional si5351_ms_afe_40m{
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.f_src = si5351_vco_afe_f, // 800 MHz
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@@ -170,6 +203,17 @@ constexpr si5351::MultisynthFractional si5351_ms_20m{
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.r_div = 0,
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};
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// constexpr auto si5351_ms_20m_reg = si5351_ms_20m.reg(0);
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// (25 MHz from 800 MHz VCO: 800 / 32 = 25)
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// Define xtal MultiSynth 25MHz clock for stable PLL B, and XTAL reference
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constexpr si5351::MultisynthFractional si5351_ms_25m{
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.f_src = si5351_vco_f, // 800,000,000 Hz
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.a = 32, // 800 / 32 = 25 MHz
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.b = 0,
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.c = 1,
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.r_div = 0 // No final bit-shifting
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};
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#endif
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constexpr auto si5351c_ms_0_8m_reg = si5351_ms_0_8m.reg(clock_generator_output_og_codec);
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@@ -294,19 +338,21 @@ constexpr ClockControls si5351c_clock_control_common{{
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constexpr ClockControls si5351a_clock_control_common{{
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#ifdef PRALINE
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// CLK0: MAX5864 (ADC) - 4mA, Normal PLLA Integer (Standard for Praline sync)
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// CLK0: MAX5864 (ADC) - 4mA, Normal PLLA Integer
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK1: SCT_CLK (iCE40 FPGA) - 6mA, PLLA Normal Integer
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK2: LPC43xx MCU - 4mA, Normal PLLB (Must be Integer for MCU stability)
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// CLK1: SCT_CLK (iCE40 FPGA) - 4mA, Normal PLLB Integer
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLB, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK3: CLKOUT SMA Port P1 - 8mA, Normal PLLB Integer
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{ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLB, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK4: MAX2831 reference (40 MHz) - Inverted PLLA Integer (Required for mixer lock)
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// CLK2: LPC43xx MCU - 2mA, Normal PLLA (Must be Integer for MCU stability)
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK3: CLKOUT SMA Port P1 - 2mA, Normal PLLB Integer Power_Off
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLB, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK4: MAX2831 reference (40 MHz) - 4mA, Invert PLLA Integer (Required for mixer lock)
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK5: RFFC5072 reference (40 MHz) - Inverted PLLA Integer (Required for mixer lock)
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK6: Not used (disabled) 2mA, Normal PLLB, Power_Off
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// CLK5: RFFC5072 reference (40 MHz) - 4mA, Invert PLLA Integer (Required for mixer lock)
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_On},
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// CLK6: Not used (disabled) 2mA, Normal PLLB Integer, Power_Off
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLB, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK7: Not used (disabled) 2mA, Normal PLLB Integer, Power_Off
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLB, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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#else
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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@@ -319,9 +365,9 @@ constexpr ClockControls si5351a_clock_control_common{{
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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// CLK6: Not used
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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#endif
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// CLK7: Not used
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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#endif
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}};
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@@ -461,20 +507,24 @@ void ClockManager::init_clock_generator() {
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* - Note: Timing for SGPIO data bus; scales to 2x SR in wideband modes.
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* * CLK2: MCU_CLKIN (LPC43xx MCU External Clock Input)
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* - Note: Synchronizes MCU processing to the RF clock tree.
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* * CLK3: SG_CLK (Switching Regulator/Internal Logic Sync)
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* * CLK3: SG_CLK (Switching Regulator/Internal Logic Sync) SMA Port 1
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* - Note: Used for internal FPGA logic/gateware synchronization.
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* * CLK4: P_CLK (Peripheral/Expansion Clock)
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* * CLK4: P_CLK (MAX2831 Peripheral/Expansion Clock)
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* - Note: Routed to expansion headers for external hardware sync.
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* * CLK5: AUX_CLK (Auxiliary reference for secondary logic)
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* * CLK5: AUX_CLK (RFFC5371 Auxiliary reference for secondary logic)
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* - Note: Provides additional timing flexibility for the iCE40 FPGA.
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* * CLK6/7: Unused / Power-Down
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* * CLK6: SG_CLK (Switching Regulator/Internal Logic Sync) SMA Port 2
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* - Note: Used for internal FPGA logic/gateware synchronization.
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* * CLK7: Unused / Power-Down
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* - State: Disabled (si5351a_ms6_7_off_reg)
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* - Note: Kept OFF to reduce EMI/RFI near the RF front-end.
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* * CLKOUT: Optional external clock output on the header.
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*/
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/* Step 1: Write PLL A (800 MHz for RF) and PLL B (800 MHz for Digital) */
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/* Use single-byte writes to debug I2C issues */
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/* Write PLL A (800 MHz based on 25 MHz xtal for RF) and
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* PLL B (800 MHZ based on 25 MHz xtalfor Digital)
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* Use single-byte writes to debug I2C issues
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*/
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{
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// Write PLLA (Registers 26-33)
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/* Write PLL A configuration (Base 26) */
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@@ -484,28 +534,31 @@ void ClockManager::init_clock_generator() {
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}
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// Write PLLB (Registers 34-41)
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/* Write PLL B configuration (Base 34) */
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const auto& pll_b = si5351_pll_b_800_reg;
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for (size_t i = 1; i < pll_b.size(); i++) {
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clock_generator.write_register(pll_b[0] + i - 1, pll_b[i]);
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}
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}
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/* Step 2: Write multisynth configurations using single-byte writes */
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/* Write multisynth configurations using single-byte writes */
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// These cover all active channels on the Praline board
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clock_generator.write_ms_single_byte(0, si5351_ms_afe_40m); // CLK0: PLL A Codec (40 MHz)
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clock_generator.write_ms_single_byte(1, si5351_ms_afe_40m); // CLK1: PLL A FPGA Timing (40 MHz)
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clock_generator.write_ms_single_byte(2, si5351_ms_40m); // CLK2: PLL B MCU Input (40 MHz)
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clock_generator.write_ms_single_byte(3, si5351_ms_10m); // CLK3: PLL B Logic Sync (10 MHz)
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clock_generator.write_ms_single_byte(4, si5351_ms_afe_40m); // CLK4: PLL A Second IF (40 MHz)
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clock_generator.write_ms_single_byte(5, si5351_ms_afe_40m); // CLK5: PLL A First IF (40 MHz)
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clock_generator.write_ms_single_byte(0, si5351_ms_afe_4m); // CLK0: PLL A AFE Codec (4 MHz)
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clock_generator.write_ms_single_byte(1, si5351_ms_10m); // CLK1: PLL B SGPIO/FPGA Timing (10 MHz)
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clock_generator.write_ms_single_byte(2, si5351_ms_afe_40m); // CLK2: PLL A Audio and MCU Input (40 MHz)
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clock_generator.write_ms_single_byte(3, si5351_ms_0_4m); // CLK3: PLL B SMA Port 1 Logic Sync (4 MHz or 10 MHz)
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clock_generator.write_ms_single_byte(4, si5351_ms_afe_40m); // CLK4: PLL A MAX2831 Second IF (40 MHz)
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clock_generator.write_ms_single_byte(5, si5351_ms_afe_40m); // CLK5: PLL A RFFC5071First IF (40 MHz)
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clock_generator.write_ms_single_byte(6, si5351_ms_0_4m); // CLK6: PLL B SMA Port 2 Logic Sync (4 MHz or 10 MHz)
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clock_generator.write_ms_single_byte(7, si5351_ms_0_4m); // CLK7: PLL B Unused (4 MHz)
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/* Step 3: NOW set clock control registers (AFTER multisynths per HackRF reference) */
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/* NOW set clock control registers (AFTER multisynths per HackRF reference) */
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const auto ref_pll_a = ClockControl::MultiSynthSource::PLLA;
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const auto ref_pll_b = ClockControl::MultiSynthSource::PLLB;
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const ClockControls si5351_clock_control = ClockControls{{
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si5351a_clock_control_common[0].ms_src(ref_pll_a),
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si5351a_clock_control_common[1].ms_src(ref_pll_a),
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si5351a_clock_control_common[2].ms_src(ref_pll_b),
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si5351a_clock_control_common[1].ms_src(ref_pll_b),
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si5351a_clock_control_common[2].ms_src(ref_pll_a),
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si5351a_clock_control_common[3].ms_src(ref_pll_b),
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si5351a_clock_control_common[4].ms_src(ref_pll_a),
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si5351a_clock_control_common[5].ms_src(ref_pll_a),
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@@ -515,6 +568,16 @@ void ClockManager::init_clock_generator() {
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// clock_generator.set_clock_control(si5351_clock_control);
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// Use single-byte writes instead of multi-byte
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clock_generator.set_clock_control_single_byte(si5351_clock_control);
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// Don't write CLKS 3, 6, and 7 multisynth
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// Ensure CLK3 clock control has Power_Off
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// Verify output is disabled
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clock_generator.disable_output(3);
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clock_generator.disable_clock(3);
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clock_generator.disable_output(6);
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clock_generator.disable_clock(6);
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clock_generator.disable_output(7);
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clock_generator.disable_clock(7);
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#else
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if (hackrf_r9) {
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const PLLReg pll_reg = (reference.source == ReferenceSource::Xtal)
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@@ -755,6 +818,9 @@ void ClockManager::set_sampling_frequency(const uint32_t frequency) {
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_resampling_n = n;
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// === Stop FPGA processing and flush filters ===
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fpga_debug_register_write(1, 0x00); // Disable FPGA filters (resets CIC accumulators)
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// Set FPGA RX decimation register
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fpga_debug_register_write(2, n);
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radio::invalidate_spi_config();
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@@ -766,6 +832,17 @@ void ClockManager::set_sampling_frequency(const uint32_t frequency) {
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clock_generator.set_ms_frequency(0, afe_rate * 2, si5351_vco_afe_f, 1);
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clock_generator.set_ms_frequency(1, afe_rate * 2, si5351_vco_afe_f, 0);
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// === Reset PLL A for phase alignment ===
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clock_generator.write_register(si5351::Register::PLLReset, 0x20);
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||||
|
||||
// Brief delay for PLL lock and clock stability ===
|
||||
// ~1ms at 96MHz = ~96000 cycles, use 10ms for safety
|
||||
volatile uint32_t delay = 240000; // ~2.5ms
|
||||
while (delay--);
|
||||
|
||||
// Re-enable FPGA processing with clean state ===
|
||||
fpga_debug_register_write(1, 0x01);
|
||||
|
||||
#else
|
||||
/* Codec clock is at sampling frequency, CPLD and SGPIO clocks are at
|
||||
* twice the frequency, and derived from the MS0 synth. So it's only
|
||||
@@ -796,7 +873,7 @@ void ClockManager::set_reference_ppb(const int32_t ppb) {
|
||||
if (reference.source == ReferenceSource::External) {
|
||||
return;
|
||||
}
|
||||
constexpr uint32_t pll_multiplier = si5351_pll_xtal_800m.a;
|
||||
constexpr uint32_t pll_multiplier = si5351_pll_a_afe_800m.a;
|
||||
#else
|
||||
constexpr uint32_t pll_multiplier = si5351_pll_xtal_25m.a;
|
||||
#endif
|
||||
@@ -834,15 +911,15 @@ void ClockManager::start_frequency_monitor_measurement(const cgu::CLK_SEL clk_se
|
||||
}
|
||||
|
||||
void ClockManager::wait_For_frequency_monitor_measurement_done() {
|
||||
// FREQ_MON mechanism fails to finish if there's no clock present on selected input?!
|
||||
#ifndef PRALINE
|
||||
while (LPC_CGU->FREQ_MON.MEAS == 1);
|
||||
#else
|
||||
// FREQ_MON mechanism fails to finish if there's no clock present on selected input?!
|
||||
#ifdef PRALINE
|
||||
// PRALINE FIX: Add timeout to prevent infinite hang
|
||||
uint32_t timeout = 100000;
|
||||
while (LPC_CGU->FREQ_MON.MEAS == 1 && timeout > 0) {
|
||||
timeout--;
|
||||
}
|
||||
#else
|
||||
while (LPC_CGU->FREQ_MON.MEAS == 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -855,7 +932,8 @@ uint32_t ClockManager::get_frequency_monitor_measurement_in_hertz() {
|
||||
|
||||
void ClockManager::start_audio_pll() {
|
||||
#ifdef PRALINE
|
||||
// Comprehensive init matches non-PRALINE for stability and source selection
|
||||
|
||||
// Control Block
|
||||
cgu::pll0audio::ctrl({
|
||||
.pd = 1, // Start powered down
|
||||
.bypass = 0, // Use the PLL
|
||||
@@ -864,19 +942,66 @@ void ClockManager::start_audio_pll() {
|
||||
.clken = 0, // Disable output initially
|
||||
.frm = 0, // Normal mode
|
||||
.autoblock = 1, // Glitchless switching
|
||||
.pllfract_req = 0, // Integer mode
|
||||
.sel_ext = 1, // MUST BE 1 to use clk_sel GP_CLKIN
|
||||
.mod_pd = 1, // Power down modulator (Reduces noise/hiss)
|
||||
.pllfract_req = 1, // Integer, Disabled
|
||||
.sel_ext = 1, // Use GP_CLKIN (CLK2)
|
||||
.mod_pd = 0, // Modulator OFF
|
||||
.clk_sel = cgu::CLK_SEL::GP_CLKIN,
|
||||
});
|
||||
|
||||
cgu::pll0audio::mdiv({.mdec = 30542UL});
|
||||
cgu::pll0audio::np_div({.pdec = 31, .ndec = 45});
|
||||
cgu::pll0audio::frac({.pllfract_ctrl = 0});
|
||||
/*
|
||||
* Audio PLL Configuration for 48 kHz audio with 256Fs MCLK
|
||||
* Target output: Fout = 12.288 MHz
|
||||
*
|
||||
* Formulas:
|
||||
* Fout = Fin × MSEL / (NSEL × PSEL)
|
||||
* FCO = 2 × Fin × MSEL / NSEL (must be 275-550 MHz)
|
||||
*/
|
||||
|
||||
/*
|
||||
* ┌─────────────────────────────────────────────────────────────────┐
|
||||
* │ 10 MHz INPUT (HackRF r9 compatible but interfere with fm band) │
|
||||
* ├─────────────────────────────────────────────────────────────────┤
|
||||
* │ MSEL=3072, NSEL=125, PSEL=20 │
|
||||
* │ Fout = 10 × 3072 / (125 × 20) = 30720 / 2500 = 12.288 MHz ✓ │
|
||||
* │ FCO = 2 × 10 × 3072 / 125 = 61440 / 125 = 491.52 MHz ✓ │
|
||||
* │ │
|
||||
* │ Encoded values: MDEC=8308, NDEC=45, PDEC=31 │
|
||||
* │ CLK2 harmonics: 90, 100, 110 MHz (interfere with FM band!) │
|
||||
* └─────────────────────────────────────────────────────────────────┘
|
||||
*/
|
||||
|
||||
/*
|
||||
// Math: (10 MHz * 3072) / (125 * 20) * 2 = 12.288MHz
|
||||
cgu::pll0audio::mdiv({.mdec = 8308UL}); // MSEL = 3072
|
||||
cgu::pll0audio::np_div({
|
||||
.pdec = 31, // PSEL = 20 for 10 MHz
|
||||
.ndec = 45 // NSEL = 125 for 10 MHz
|
||||
});
|
||||
*/
|
||||
|
||||
/*
|
||||
* ┌─────────────────────────────────────────────────────────────────┐
|
||||
* │ 40 MHz INPUT (Recommended - avoids FM band harmonics) │
|
||||
* ├─────────────────────────────────────────────────────────────────┤
|
||||
* │ MSEL=768, NSEL=125, PSEL=20 │
|
||||
* │ Fout = 40 × 768 / (125 × 20) = 30720 / 2500 = 12.288 MHz ✓ │
|
||||
* │ FCO = 2 × 40 × 768 / 125 = 61440 / 125 = 491.52 MHz ✓ │
|
||||
* │ │
|
||||
* │ Encoded values: MDEC=30542, NDEC=45, PDEC=31 │
|
||||
* │ CLK2 harmonics: 80, 120, 160 MHz (none in FM 88-108 MHz band) │
|
||||
* └─────────────────────────────────────────────────────────────────┘
|
||||
*/
|
||||
|
||||
// 40 MHz input → 12.288 MHz output (same as HackRF OG)
|
||||
// Math: (40MHz * 768) / (125 * 20) * 2 = 12.288MHz
|
||||
cgu::pll0audio::mdiv({.mdec = 30542UL}); // MSEL = 768
|
||||
cgu::pll0audio::np_div({.pdec = 31,
|
||||
.ndec = 45});
|
||||
|
||||
cgu::pll0audio::frac({.pllfract_ctrl = 0});
|
||||
cgu::pll0audio::power_up();
|
||||
|
||||
// Safety timeout prevents boot hang if Si5351 clock is missing
|
||||
// Lock and Routing (Keep as is)
|
||||
{
|
||||
uint32_t timeout = 100000;
|
||||
while (!cgu::pll0audio::is_locked() && timeout > 0) {
|
||||
@@ -889,6 +1014,7 @@ void ClockManager::start_audio_pll() {
|
||||
|
||||
LPC_CGU->BASE_AUDIO_CLK.AUTOBLOCK = 1;
|
||||
LPC_CGU->BASE_AUDIO_CLK.CLK_SEL = toUType(cgu::CLK_SEL::IDIVD);
|
||||
|
||||
#else
|
||||
cgu::pll0audio::ctrl({
|
||||
.pd = 1,
|
||||
|
||||
Reference in New Issue
Block a user