HackRF Pro (praline) arch-port initial PR (#2958)

* Initial commit and pr for HackRF Pro (praline) arch-port to mayhem-firmware. Please see https://github.com/portapack-mayhem/mayhem-firmware/issues/2957. Added flash specifics for -DBOARD=PRALINE. This firmware only builds with toolchain v9.2.1 if hackrf codebase has -B arm in firmware/hackrf_usb/CMakeLists.txt.

* Updated CMakeLists.txt per coordination with @HtoToo. For -DBOARD=PRALINE FLASH_MB_SIZE and FLASH_MB_LIMIT_SIZE are now 4. Removed praline specific variable for FLASH limits.

* Updated chibios-portapack's board.cpp to support initialization of the HachRF-Pro (praline) FPGA. Added append_fpga_bitstream.py tool to ensure that praline_fgpa.bin bitstream can be appended to -DBOARD=PRALINE produced firmware. In order to ensure successful execution of append_fpga_bitstream.py to append the fpga bitstream we should expect that the bistsream will be located at 0x180000 in flash. This requires that FLASH_MB_LIMIT_SIZE must be 1.5, and FLASH_BYTES_LIMIT_SIZE must be 1535 * 1024. If we want to allow more or less space for the base firmware image sans the fpga bitstream the location of the bistream must be moved to a location other than 0x180000.

* Updated location of praline_fpga.bin bitstream to 0x380000 to allow more room for firmware. Firmware now has 3.5MB, or 2MB more available than before as coordinated with @HTotoo.

* Expanded #ifndef PRALINE to include og and r9 gpio and pin setup as coordinated with @HTotoo.

* Added note for PRALINE FLASH_MB_LIMIT_SIZE and FLASH_BYTES_LIMIT_SIZE to explain why we are using the 3.5 and 3584 values respectively as coordinated with @HTotoo.

* Next round of modifications derived heavily, if not entirely  from work done by @banandana at https://github.com/Banandana/mayhem-firmware. This commit should power on the HackRF Pro (praline) display, power on the fpga, and enable gpio, and provide debug utilties. There is still a lot of work to be done to fully enable the new praline board with this build and firmware architectural porting effort. However, hackrf-one boards do not seem to be adversely impacted by the #ifdef PRALINE statements, and CMakeLists updates, as far as I have been able to test.

* Ran format-code.sh. Updates for this commit are only due to formatting. Tested builds and they seem to work as exptected.

* Addressed fixes in firmware/application and firmware/baseband. Stream now flows to capture and looking glass. Issues were related to thread management. Issues were originally addressed by @banandana.

* Ran format-code.sh to allow for consistency with autoamted clang checks.

* Update hackrf ref repo to mayhem-portapack-hackrf next from https://github.com/portapack-mayhem/hackrf

* Addressed format edits necessary to pass clang-format check.

* Starting addressing Si5351 Clocks for radio sampling. These updates correctly set the Si5351 clock at start up. There appears to be an issue during runtime when testing with RX Test Init, Capture and Looking glass.

* Updated clock_manager.cpp to restore correct function introduced by @banandana when testing with Rx Test Init.

* Switched to using decimation for setting the sample rate without changing the Si5351 clock. This assumes that for the praline board Si5351 CLK0 runs at fixed 8 MHz (constant) and the FPGA decimates to get the desired sample rate. For example, for a 1 MHz sample rate -> Si5351 outputs 8 MHz, FPGA decimates by 8. There is still more work needed here, and potential verification that this is the correct way to operate with this new archteitecture.

* After deliberating on hackrf_usb hackrf_core.c and radio.c, and reviewing firmware/application/hw/si5351.cpp the original approach of using the aproach detailed in hackrf_core.c sample_rate_frac_set() lines 580-582, via the implementation in firmware/application/hw/si5351.cpp seems like the best place to continue testing efforts.

* Tested at ~2.4GHz (2.3 - 2.5) with lookgin glass and was able to receive signals. Added a Signal Path debug app to test gains, and readio mode (receive/transmit).

* Added two debug apps for the RFFC507x. Status View and Tuning View. This helped debug some of the potential issues with tuning.

* update submodule

* format code

* Small touch up merging latest next and ensuring build for HackRF One.

* Reverted edits to re: firmware/baseband/sd_over_usb/scsi.c and firmware/application/portapack.cpp. Source now builds, had to pull latest hackrf submodule.

* Skipped detect hardware for praline board to avoid backscreen in HackRF Pro praline board.

---------

Co-authored-by: gullradriel <gullradriel@users.noreply.github.com>

firmware/common/baseband_sgpio.cpp

@@ -189,6 +189,7 @@ constexpr uint32_t gpio_outreg(const Direction direction) {
 
 constexpr uint32_t gpio_oenreg(const Direction direction) {
     return (0U << PIN_P78) | (0U << PIN_P81) | (0U << PIN_SYNC_EN) | (0U << PIN_INVERT) | (1U << PIN_DIRECTION) | (1U << PIN_DISABLE) | (0U << PIN_CAPTURE) | (0U << PIN_CLKIN) | ((direction == Direction::Transmit) ? 0xffU : 0x00U);
+    // ^^^^^^^^^^^^^ REVERTED: SGPIO14 must be DISABLED - enabling it blocks data capture!
 }
 
 constexpr uint32_t out_mux_cfg(const P_OUT_CFG out, const P_OE_CFG oe) {
@@ -198,13 +199,23 @@ constexpr uint32_t out_mux_cfg(const P_OUT_CFG out, const P_OE_CFG oe) {
 constexpr uint32_t data_sgpio_mux_cfg(
     const CONCAT_ENABLE concat_enable,
     const CONCAT_ORDER concat_order) {
+#ifndef PRALINE
     return (1U << 0) | (0U << 1) | (0U << 3) | (3U << 5) | (1U << 7) | (0U << 9) | (toUType(concat_enable) << 11) | (toUType(concat_order) << 12);
+#else
+    return (1U << 0) | (0U << 1) | (3U << 3) | (3U << 5) | (1U << 7) | (0U << 9) | (toUType(concat_enable) << 11) | (toUType(concat_order) << 12);
+    // Bits 3-4: CLK_SOURCE_SLICE_MODE = 3 (slice D as clock source for data slices)
+#endif
 }
 
 constexpr uint32_t data_slice_mux_cfg(
     const PARALLEL_MODE parallel_mode,
     const CLK_CAPTURE_MODE clk_capture_mode) {
+#ifndef PRALINE
     return (0U << 0) | (toUType(clk_capture_mode) << 1) | (1U << 2) | (0U << 3) | (0U << 4) | (toUType(parallel_mode) << 6) | (0U << 8);
+#else
+    return (0U << 0) | (toUType(clk_capture_mode) << 1) | (1U << 2) | (0U << 3) | (1U << 4) | (toUType(parallel_mode) << 6) | (0U << 8);
+    // Bit 4 CLKGEN_MODE: 0=internal counter, 1=external clock (REQUIRED for PRALINE!)
+#endif
 }
 
 constexpr uint32_t pos(
@@ -264,28 +275,54 @@ void SGPIO::init() {
 void SGPIO::configure(const Direction direction) {
     disable_all_slice_counters();
 
+#ifndef PRALINE
     // Set data pins as input, temporarily.
     LPC_SGPIO->GPIO_OENREG = gpio_oenreg(Direction::Receive);
 
     // Now that data pins are inputs, safe to change CPLD direction.
+#endif
+
+    // HackRF reference: Set GPIO_OUTREG first (DISABLE=HIGH during config)
     LPC_SGPIO->GPIO_OUTREG = gpio_outreg(direction);
 
+#ifdef PRALINE
+    // HackRF reference: Set GPIO_OENREG ONCE before OUT_MUX_CFG (not twice!)
+    LPC_SGPIO->GPIO_OENREG = gpio_oenreg(direction);
+
+    // Now configure OUT_MUX_CFG (HackRF order: control pins first, then data pins)
+#endif
+
     LPC_SGPIO->OUT_MUX_CFG[8] = out_mux_cfg(P_OUT_CFG::DOUT_DOUTM1, P_OE_CFG::GPIO_OE);
     LPC_SGPIO->OUT_MUX_CFG[9] = out_mux_cfg(P_OUT_CFG::DOUT_DOUTM1, P_OE_CFG::GPIO_OE);
+
+#ifndef PRALINE
+    // OUT_MUX_CFG[10] NOT configured for PRALINE - breaks PRALINE (HOST_DISABLE signal)
     LPC_SGPIO->OUT_MUX_CFG[10] = out_mux_cfg(P_OUT_CFG::GPIO_OUT, P_OE_CFG::GPIO_OE);
+#endif
+
     LPC_SGPIO->OUT_MUX_CFG[11] = out_mux_cfg(P_OUT_CFG::GPIO_OUT, P_OE_CFG::GPIO_OE);
+#ifndef PRALINE
+    // SGPIO 12 and 13 are NOT configured - not used per HackRF reference for PRALINE
     LPC_SGPIO->OUT_MUX_CFG[12] = out_mux_cfg(P_OUT_CFG::GPIO_OUT, P_OE_CFG::GPIO_OE);
     LPC_SGPIO->OUT_MUX_CFG[13] = out_mux_cfg(P_OUT_CFG::GPIO_OUT, P_OE_CFG::GPIO_OE);
+#endif
+
     LPC_SGPIO->OUT_MUX_CFG[14] = out_mux_cfg(P_OUT_CFG::DOUT_DOUTM1, P_OE_CFG::GPIO_OE);
+
+#ifndef PRALINE
+    // SGPIO 15 is NOT configured - not used per HackRF reference for PRALINE
     LPC_SGPIO->OUT_MUX_CFG[15] = out_mux_cfg(P_OUT_CFG::GPIO_OUT, P_OE_CFG::GPIO_OE);
+#endif
 
     const auto data_out_mux_cfg = out_mux_cfg(data_p_out_cfg(slice_mode_multislice), P_OE_CFG::GPIO_OE);
     for (size_t i = 0; i < 8; i++) {
         LPC_SGPIO->OUT_MUX_CFG[i] = data_out_mux_cfg;
     }
 
+#ifndef PRALINE
     // Now that output enable sources are set, enable data bus in correct direction.
     LPC_SGPIO->GPIO_OENREG = gpio_oenreg(direction);
+#endif
 
     const auto slice_gpdma = Slice::H;
 
@@ -293,7 +330,25 @@ void SGPIO::configure(const Direction direction) {
     const auto clk_capture_mode = data_clk_capture_mode(direction);
     const auto single_slice = !slice_mode_multislice;
 
+#ifndef PRALINE
     uint32_t slice_enable_mask = 0;
+#endif
+
+#ifdef PRALINE
+    // Configure slice D as clock generator (REQUIRED for PRALINE!)
+    // Reference: HackRF sgpio.c line 193
+    const auto slice_d = toUType(Slice::D);
+    LPC_SGPIO->SGPIO_MUX_CFG[slice_d] = (1U << 0) | (0U << 1) | (0U << 3) | (3U << 5) | (1U << 7) | (0U << 9) | (0U << 11) | (0U << 12);
+    LPC_SGPIO->SLICE_MUX_CFG[slice_d] = (0U << 0) | (0U << 1) | (0U << 2) | (0U << 3) | (1U << 4) | (0U << 6) | (0U << 8);  // CLKGEN_MODE=1
+    LPC_SGPIO->PRESET[slice_d] = 0;
+    LPC_SGPIO->COUNT[slice_d] = 0;
+    LPC_SGPIO->POS[slice_d] = pos(0x1f, 0x1f);
+    LPC_SGPIO->REG[slice_d] = 0x11111111;
+    LPC_SGPIO->REG_SS[slice_d] = 0x11111111;
+
+    uint32_t slice_enable_mask = (1U << slice_d);  // Start with slice D enabled
+#endif
+
     for (size_t i = 0; i < slice_count; i++) {
         const auto slice = slice_order[i];
         const auto slice_index = toUType(slice);