HackRF Pro (praline) arch-port initial PR (#2958)

* Initial commit and pr for HackRF Pro (praline) arch-port to mayhem-firmware. Please see https://github.com/portapack-mayhem/mayhem-firmware/issues/2957. Added flash specifics for -DBOARD=PRALINE. This firmware only builds with toolchain v9.2.1 if hackrf codebase has -B arm in firmware/hackrf_usb/CMakeLists.txt. * Updated CMakeLists.txt per coordination with @HtoToo. For -DBOARD=PRALINE FLASH_MB_SIZE and FLASH_MB_LIMIT_SIZE are now 4. Removed praline specific variable for FLASH limits. * Updated chibios-portapack's board.cpp to support initialization of the HachRF-Pro (praline) FPGA. Added append_fpga_bitstream.py tool to ensure that praline_fgpa.bin bitstream can be appended to -DBOARD=PRALINE produced firmware. In order to ensure successful execution of append_fpga_bitstream.py to append the fpga bitstream we should expect that the bistsream will be located at 0x180000 in flash. This requires that FLASH_MB_LIMIT_SIZE must be 1.5, and FLASH_BYTES_LIMIT_SIZE must be 1535 * 1024. If we want to allow more or less space for the base firmware image sans the fpga bitstream the location of the bistream must be moved to a location other than 0x180000. * Updated location of praline_fpga.bin bitstream to 0x380000 to allow more room for firmware. Firmware now has 3.5MB, or 2MB more available than before as coordinated with @HTotoo. * Expanded #ifndef PRALINE to include og and r9 gpio and pin setup as coordinated with @HTotoo. * Added note for PRALINE FLASH_MB_LIMIT_SIZE and FLASH_BYTES_LIMIT_SIZE to explain why we are using the 3.5 and 3584 values respectively as coordinated with @HTotoo. * Next round of modifications derived heavily, if not entirely from work done by @banandana at https://github.com/Banandana/mayhem-firmware. This commit should power on the HackRF Pro (praline) display, power on the fpga, and enable gpio, and provide debug utilties. There is still a lot of work to be done to fully enable the new praline board with this build and firmware architectural porting effort. However, hackrf-one boards do not seem to be adversely impacted by the #ifdef PRALINE statements, and CMakeLists updates, as far as I have been able to test. * Ran format-code.sh. Updates for this commit are only due to formatting. Tested builds and they seem to work as exptected. * Addressed fixes in firmware/application and firmware/baseband. Stream now flows to capture and looking glass. Issues were related to thread management. Issues were originally addressed by @banandana. * Ran format-code.sh to allow for consistency with autoamted clang checks. * Update hackrf ref repo to mayhem-portapack-hackrf next from https://github.com/portapack-mayhem/hackrf * Addressed format edits necessary to pass clang-format check. * Starting addressing Si5351 Clocks for radio sampling. These updates correctly set the Si5351 clock at start up. There appears to be an issue during runtime when testing with RX Test Init, Capture and Looking glass. * Updated clock_manager.cpp to restore correct function introduced by @banandana when testing with Rx Test Init. * Switched to using decimation for setting the sample rate without changing the Si5351 clock. This assumes that for the praline board Si5351 CLK0 runs at fixed 8 MHz (constant) and the FPGA decimates to get the desired sample rate. For example, for a 1 MHz sample rate -> Si5351 outputs 8 MHz, FPGA decimates by 8. There is still more work needed here, and potential verification that this is the correct way to operate with this new archteitecture. * After deliberating on hackrf_usb hackrf_core.c and radio.c, and reviewing firmware/application/hw/si5351.cpp the original approach of using the aproach detailed in hackrf_core.c sample_rate_frac_set() lines 580-582, via the implementation in firmware/application/hw/si5351.cpp seems like the best place to continue testing efforts. * Tested at ~2.4GHz (2.3 - 2.5) with lookgin glass and was able to receive signals. Added a Signal Path debug app to test gains, and readio mode (receive/transmit). * Added two debug apps for the RFFC507x. Status View and Tuning View. This helped debug some of the potential issues with tuning. * update submodule * format code * Small touch up merging latest next and ensuring build for HackRF One. * Reverted edits to re: firmware/baseband/sd_over_usb/scsi.c and firmware/application/portapack.cpp. Source now builds, had to pull latest hackrf submodule. * Skipped detect hardware for praline board to avoid backscreen in HackRF Pro praline board. --------- Co-authored-by: gullradriel <gullradriel@users.noreply.github.com>
2026-09-09 08:19:07 +00:00 · 2026-02-11 03:15:11 -05:00
parent cd30022b61
commit 39424632bb
50 changed files with 4822 additions and 48 deletions
@@ -189,6 +189,7 @@ constexpr uint32_t gpio_outreg(const Direction direction) {

 constexpr uint32_t gpio_oenreg(const Direction direction) {
    return (0U << PIN_P78) | (0U << PIN_P81) | (0U << PIN_SYNC_EN) | (0U << PIN_INVERT) | (1U << PIN_DIRECTION) | (1U << PIN_DISABLE) | (0U << PIN_CAPTURE) | (0U << PIN_CLKIN) | ((direction == Direction::Transmit) ? 0xffU : 0x00U);
+    // ^^^^^^^^^^^^^ REVERTED: SGPIO14 must be DISABLED - enabling it blocks data capture!
 }

 constexpr uint32_t out_mux_cfg(const P_OUT_CFG out, const P_OE_CFG oe) {
@@ -198,13 +199,23 @@ constexpr uint32_t out_mux_cfg(const P_OUT_CFG out, const P_OE_CFG oe) {
 constexpr uint32_t data_sgpio_mux_cfg(
    const CONCAT_ENABLE concat_enable,
    const CONCAT_ORDER concat_order) {
+#ifndef PRALINE
    return (1U << 0) | (0U << 1) | (0U << 3) | (3U << 5) | (1U << 7) | (0U << 9) | (toUType(concat_enable) << 11) | (toUType(concat_order) << 12);
+#else
+    return (1U << 0) | (0U << 1) | (3U << 3) | (3U << 5) | (1U << 7) | (0U << 9) | (toUType(concat_enable) << 11) | (toUType(concat_order) << 12);
+    // Bits 3-4: CLK_SOURCE_SLICE_MODE = 3 (slice D as clock source for data slices)
+#endif
 }

 constexpr uint32_t data_slice_mux_cfg(
    const PARALLEL_MODE parallel_mode,
    const CLK_CAPTURE_MODE clk_capture_mode) {
+#ifndef PRALINE
    return (0U << 0) | (toUType(clk_capture_mode) << 1) | (1U << 2) | (0U << 3) | (0U << 4) | (toUType(parallel_mode) << 6) | (0U << 8);
+#else
+    return (0U << 0) | (toUType(clk_capture_mode) << 1) | (1U << 2) | (0U << 3) | (1U << 4) | (toUType(parallel_mode) << 6) | (0U << 8);
+    // Bit 4 CLKGEN_MODE: 0=internal counter, 1=external clock (REQUIRED for PRALINE!)
+#endif
 }

 constexpr uint32_t pos(
@@ -264,28 +275,54 @@ void SGPIO::init() {
 void SGPIO::configure(const Direction direction) {
    disable_all_slice_counters();

+#ifndef PRALINE
    // Set data pins as input, temporarily.
    LPC_SGPIO->GPIO_OENREG = gpio_oenreg(Direction::Receive);

    // Now that data pins are inputs, safe to change CPLD direction.
+#endif
+
+    // HackRF reference: Set GPIO_OUTREG first (DISABLE=HIGH during config)
    LPC_SGPIO->GPIO_OUTREG = gpio_outreg(direction);

+#ifdef PRALINE
+    // HackRF reference: Set GPIO_OENREG ONCE before OUT_MUX_CFG (not twice!)
+    LPC_SGPIO->GPIO_OENREG = gpio_oenreg(direction);
+
+    // Now configure OUT_MUX_CFG (HackRF order: control pins first, then data pins)
+#endif
+
    LPC_SGPIO->OUT_MUX_CFG[8] = out_mux_cfg(P_OUT_CFG::DOUT_DOUTM1, P_OE_CFG::GPIO_OE);
    LPC_SGPIO->OUT_MUX_CFG[9] = out_mux_cfg(P_OUT_CFG::DOUT_DOUTM1, P_OE_CFG::GPIO_OE);
+
+#ifndef PRALINE
+    // OUT_MUX_CFG[10] NOT configured for PRALINE - breaks PRALINE (HOST_DISABLE signal)
    LPC_SGPIO->OUT_MUX_CFG[10] = out_mux_cfg(P_OUT_CFG::GPIO_OUT, P_OE_CFG::GPIO_OE);
+#endif
+
    LPC_SGPIO->OUT_MUX_CFG[11] = out_mux_cfg(P_OUT_CFG::GPIO_OUT, P_OE_CFG::GPIO_OE);
+#ifndef PRALINE
+    // SGPIO 12 and 13 are NOT configured - not used per HackRF reference for PRALINE
    LPC_SGPIO->OUT_MUX_CFG[12] = out_mux_cfg(P_OUT_CFG::GPIO_OUT, P_OE_CFG::GPIO_OE);
    LPC_SGPIO->OUT_MUX_CFG[13] = out_mux_cfg(P_OUT_CFG::GPIO_OUT, P_OE_CFG::GPIO_OE);
+#endif
+
    LPC_SGPIO->OUT_MUX_CFG[14] = out_mux_cfg(P_OUT_CFG::DOUT_DOUTM1, P_OE_CFG::GPIO_OE);
+
+#ifndef PRALINE
+    // SGPIO 15 is NOT configured - not used per HackRF reference for PRALINE
    LPC_SGPIO->OUT_MUX_CFG[15] = out_mux_cfg(P_OUT_CFG::GPIO_OUT, P_OE_CFG::GPIO_OE);
+#endif

    const auto data_out_mux_cfg = out_mux_cfg(data_p_out_cfg(slice_mode_multislice), P_OE_CFG::GPIO_OE);
    for (size_t i = 0; i < 8; i++) {
        LPC_SGPIO->OUT_MUX_CFG[i] = data_out_mux_cfg;
    }

+#ifndef PRALINE
    // Now that output enable sources are set, enable data bus in correct direction.
    LPC_SGPIO->GPIO_OENREG = gpio_oenreg(direction);
+#endif

    const auto slice_gpdma = Slice::H;

@@ -293,7 +330,25 @@ void SGPIO::configure(const Direction direction) {
    const auto clk_capture_mode = data_clk_capture_mode(direction);
    const auto single_slice = !slice_mode_multislice;

+#ifndef PRALINE
    uint32_t slice_enable_mask = 0;
+#endif
+
+#ifdef PRALINE
+    // Configure slice D as clock generator (REQUIRED for PRALINE!)
+    // Reference: HackRF sgpio.c line 193
+    const auto slice_d = toUType(Slice::D);
+    LPC_SGPIO->SGPIO_MUX_CFG[slice_d] = (1U << 0) | (0U << 1) | (0U << 3) | (3U << 5) | (1U << 7) | (0U << 9) | (0U << 11) | (0U << 12);
+    LPC_SGPIO->SLICE_MUX_CFG[slice_d] = (0U << 0) | (0U << 1) | (0U << 2) | (0U << 3) | (1U << 4) | (0U << 6) | (0U << 8);  // CLKGEN_MODE=1
+    LPC_SGPIO->PRESET[slice_d] = 0;
+    LPC_SGPIO->COUNT[slice_d] = 0;
+    LPC_SGPIO->POS[slice_d] = pos(0x1f, 0x1f);
+    LPC_SGPIO->REG[slice_d] = 0x11111111;
+    LPC_SGPIO->REG_SS[slice_d] = 0x11111111;
+
+    uint32_t slice_enable_mask = (1U << slice_d);  // Start with slice D enabled
+#endif
+
    for (size_t i = 0; i < slice_count; i++) {
        const auto slice = slice_order[i];
        const auto slice_index = toUType(slice);
@@ -41,8 +41,14 @@ constexpr GPIO gpio_led_tx = gpio[GPIO2_8];
 constexpr GPIO gpio_og_1v8_enable = gpio[GPIO3_6];
 constexpr GPIO gpio_r9_1v8_enable = gpio[GPIO2_9];
 constexpr GPIO gpio_vregmode = gpio[GPIO3_7];
+#ifdef PRALINE
+// PRALINE uses different power control pins
+constexpr GPIO gpio_og_vaa_disable = gpio[GPIO4_1];  // PRALINE VAA disable (P8_1)
+constexpr GPIO gpio_r9_vaa_disable = gpio[GPIO4_1];  // PRALINE VAA disable (P8_1)
+#else
 constexpr GPIO gpio_og_vaa_disable = gpio[GPIO2_9];
 constexpr GPIO gpio_r9_vaa_disable = gpio[GPIO3_6];
+#endif

 constexpr GPIO gpio_rx_mix_bp = gpio[GPIO2_12];
 constexpr GPIO gpio_tx_mix_bp = gpio[GPIO2_11];
@@ -64,19 +70,80 @@ constexpr GPIO gpio_not_tx_amp_pwr = gpio[GPIO3_5];

 constexpr GPIO gpio_rffc5072_resetx = gpio[GPIO2_14];
 constexpr GPIO gpio_rffc5072_select = gpio[GPIO2_13];
+#ifdef PRALINE
+constexpr GPIO gpio_rffc5072_clock = gpio[GPIO5_18];
+constexpr GPIO gpio_rffc5072_data = gpio[GPIO4_14];
+#else
 constexpr GPIO gpio_rffc5072_clock = gpio[GPIO5_6];
 constexpr GPIO gpio_rffc5072_data = gpio[GPIO3_3];
+#endif

+#ifdef PRALINE
+constexpr GPIO gpio_max283x_select = gpio[GPIO6_28];
+#else
 constexpr GPIO gpio_max283x_select = gpio[GPIO0_15];
+#endif
+
+#ifdef PRALINE
+// PRALINE uses MAX2831 transceiver with different control pins
+constexpr GPIO gpio_max283x_enable = gpio[GPIO7_1];     // MAX2831 ENABLE (PE_1)
+constexpr GPIO gpio_max2831_enable = gpio[GPIO7_1];     // Alias
+constexpr GPIO gpio_max2831_rx_enable = gpio[GPIO7_2];  // MAX2831 RX_ENABLE (PE_2)
+constexpr GPIO gpio_max2831_rxhp = gpio[GPIO6_29];      // MAX2831 RXHP (PD_15)
+constexpr GPIO gpio_max2831_ld = gpio[GPIO4_11];        // MAX2831 Lock Detect (P9_6)
+// Legacy aliases for code compatibility
+constexpr GPIO gpio_max2837_rxenable = gpio[GPIO7_2];
+constexpr GPIO gpio_max2837_txenable = gpio[GPIO7_2];  // MAX2831 uses single RX/TX control
+constexpr GPIO gpio_max2839_rxtx = gpio[GPIO7_2];
+#else
 constexpr GPIO gpio_max283x_enable = gpio[GPIO2_6];
 constexpr GPIO gpio_max2837_rxenable = gpio[GPIO2_5];
 constexpr GPIO gpio_max2837_txenable = gpio[GPIO2_4];
 constexpr GPIO gpio_max2839_rxtx = gpio[GPIO2_5];
+#endif

+#ifdef PRALINE
+constexpr GPIO gpio_max5864_select = gpio[GPIO6_30];
+constexpr GPIO gpio_fpga_select = gpio[GPIO2_10];  // FPGA SPI CS (P5_1)
+#else
 constexpr GPIO gpio_max5864_select = gpio[GPIO2_7];
+#endif

 constexpr GPIO gpio_q_invert = gpio[GPIO0_13];

+#ifdef PRALINE
+// PRALINE power control
+constexpr GPIO gpio_vaa_disable = gpio[GPIO4_1];      // VAA disable (P8_1)
+constexpr GPIO gpio_1v2_enable = gpio[GPIO4_7];       // 1V2 enable (P8_7)
+constexpr GPIO gpio_3v3aux_disable = gpio[GPIO5_15];  // 3V3 aux disable (P6_7)
+
+// PRALINE RF path control
+constexpr GPIO gpio_tx_enable = gpio[GPIO3_4];          // TX enable (P6_5)
+constexpr GPIO gpio_mix_enable_n = gpio[GPIO3_2];       // Mixer enable inverted (P6_3)
+constexpr GPIO gpio_lpf_enable = gpio[GPIO4_8];         // LPF enable (PA_1)
+constexpr GPIO gpio_rf_amp_enable = gpio[GPIO4_9];      // RF amp enable (PA_2)
+constexpr GPIO gpio_ant_bias_disable = gpio[GPIO1_12];  // Antenna bias disable (P2_12)
+
+// PRALINE mixer lock detect (gpio_max2831_ld defined above at line 93)
+constexpr GPIO gpio_rffc5072_ld = gpio[GPIO6_25];  // Mixer lock detect (PD_11)
+
+// PRALINE LED4
+constexpr GPIO gpio_led4 = gpio[GPIO4_6];  // LED4 (P8_6)
+
+// PRALINE dual port control
+constexpr GPIO gpio_p1_ctrl0 = gpio[GPIO0_14];    // P1 control 0 (P2_10)
+constexpr GPIO gpio_p1_ctrl1 = gpio[GPIO5_16];    // P1 control 1 (P6_8)
+constexpr GPIO gpio_p1_ctrl2 = gpio[GPIO3_5];     // P1 control 2 (P6_9)
+constexpr GPIO gpio_p2_ctrl0 = gpio[GPIO7_3];     // P2 control 0 (PE_3)
+constexpr GPIO gpio_p2_ctrl1 = gpio[GPIO7_4];     // P2 control 1 (PE_4)
+constexpr GPIO gpio_clkin_ctrl = gpio[GPIO0_15];  // CLKIN control (P1_20)
+
+// PRALINE trigger/sync I/O
+constexpr GPIO gpio_trigger_in = gpio[GPIO6_26];  // Trigger input (PD_12)
+constexpr GPIO gpio_trigger_out = gpio[GPIO5_6];  // Trigger output (P2_6)
+constexpr GPIO gpio_pps_out = gpio[GPIO5_5];      // PPS output (P2_5)
+#endif
+
 constexpr GPIO gpio_cpld_tdo = gpio[GPIO5_18];
 constexpr GPIO gpio_cpld_tck = gpio[GPIO3_0];
 constexpr GPIO gpio_cpld_tms = gpio[GPIO3_4];
@@ -62,8 +62,16 @@ constexpr size_t clock_generator_output_og_codec = 0;
 constexpr size_t clock_generator_output_og_cpld = 1;
 constexpr size_t clock_generator_output_og_sgpio = 2;
 constexpr size_t clock_generator_output_og_clkout = 3;
+#ifdef PRALINE
+/* PRALINE has swapped CLK4/CLK5 vs HackRF One OG:
+ * CLK4 = XCVR_CLK (MAX2831) = second IF
+ * CLK5 = MIX_CLK (RFFC5072) = first IF */
+constexpr size_t clock_generator_output_og_first_if = 5;   // RFFC5072 on CLK5
+constexpr size_t clock_generator_output_og_second_if = 4;  // MAX2831 on CLK4
+#else
 constexpr size_t clock_generator_output_og_first_if = 4;
 constexpr size_t clock_generator_output_og_second_if = 5;
+#endif
 constexpr size_t clock_generator_output_og_mcu_clkin = 7;

 constexpr size_t clock_generator_output_r9_if = 0;
@@ -110,4 +110,4 @@ class I2CDevManager {
 };
 };  // namespace i2cdev

-#endif
+#endif
@@ -30,17 +30,30 @@ struct LED {
    }

    void setup() const {
+#ifdef PRALINE
+        /* PRALINE LEDs are active-low (GPIO LOW = LED ON) */
+        _gpio.set(); /* Start with LED OFF (HIGH) */
+#else
        _gpio.clear();
+#endif
        _gpio.output();
        _gpio.configure();
    }

    void on() const {
+#ifdef PRALINE
+        _gpio.clear(); /* LOW = ON for PRALINE */
+#else
        _gpio.set();
+#endif
    }

    void off() const {
+#ifdef PRALINE
+        _gpio.set(); /* HIGH = OFF for PRALINE */
+#else
        _gpio.clear();
+#endif
    }

    void toggle() const {
@@ -48,7 +61,11 @@ struct LED {
    }

    void write(const bool value) const {
+#ifdef PRALINE
+        _gpio.write(!value); /* Invert for PRALINE */
+#else
        _gpio.write(value);
+#endif
    }

   private:
@@ -109,6 +109,29 @@ enum Pins {
    P7_7,
    P9_5,
    P9_6,
+#ifdef PRALINE
+    P9_2,
+    // Port A pins (PRALINE RF path control)
+    PA_1,
+    PA_2,
+    // Port 8 pins (PRALINE power control and LED4)
+    P8_1,
+    P8_6,
+    P8_7,
+    // Port E pins (PRALINE transceiver control)
+    PE_1,
+    PE_2,
+    PE_3,
+    PE_4,
+    // Port D pins (PRALINE - GPIO-only high-drive pins)
+    // These use SCU_SFSPD registers, not normal SFSP
+    // SCU configuration must be done separately in board.cpp
+    PD_11,
+    PD_12,
+    PD_14,
+    PD_15,
+    PD_16,
+#endif
    PF_4,
    CLK0,
    CLK2,
@@ -197,6 +220,28 @@ constexpr Pin pins[]{
    [P7_7] = {7, 7},
    [P9_5] = {9, 5},
    [P9_6] = {9, 6},
+#ifdef PRALINE
+    [P9_2] = {9, 2},
+    // Port A pins (function 0 = GPIO)
+    [PA_1] = {0xA, 1},
+    [PA_2] = {0xA, 2},
+    // Port 8 pins
+    [P8_1] = {8, 1},
+    [P8_6] = {8, 6},
+    [P8_7] = {8, 7},
+    // Port E pins (function 4 = GPIO)
+    [PE_1] = {0xE, 1},
+    [PE_2] = {0xE, 2},
+    [PE_3] = {0xE, 3},
+    [PE_4] = {0xE, 4},
+    // Port D pins - GPIO-only, no pin mux needed
+    // Using 0xD as marker for Port D (SCU_SFSPD registers)
+    [PD_11] = {0xD, 11},
+    [PD_12] = {0xD, 12},
+    [PD_14] = {0xD, 14},
+    [PD_15] = {0xD, 15},
+    [PD_16] = {0xD, 16},
+#endif
    [PF_4] = {15, 4},
    [CLK0] = {24, 0},
    [CLK2] = {24, 2},
@@ -209,7 +254,8 @@ enum GPIOs {
    GPIO0_3,
    GPIO0_4,
    GPIO0_5,
-    /*GPIO0_6,*/ GPIO0_7,
+    /*GPIO0_6,*/
+    GPIO0_7,
    GPIO0_8,
    GPIO0_9,
    GPIO0_10,
@@ -275,12 +321,35 @@ enum GPIOs {
    GPIO5_7,
    GPIO5_8,
    GPIO5_9,
-    /*GPIO5_10, GPIO5_11,*/ GPIO5_12,
+    /*GPIO5_10, GPIO5_11,*/
+    GPIO5_12,
    GPIO5_13,
    GPIO5_14,
    GPIO5_15,
    GPIO5_16,
    GPIO5_18,
+    // PRALINE-specific GPIOs (always defined to avoid compile-time array gaps)
+    // RFFC5072 mixer data
+    GPIO4_14,
+    // Power control and LED4
+    GPIO4_1,
+    GPIO4_6,
+    GPIO4_7,
+    // RF path control
+    GPIO4_8,
+    GPIO4_9,
+    // Transceiver (MAX2831) control
+    GPIO7_1,
+    GPIO7_2,
+    // Dual port control
+    GPIO7_3,
+    GPIO7_4,
+    // GPIO6 (Port D pins)
+    GPIO6_25,
+    GPIO6_26,
+    GPIO6_28,
+    GPIO6_29,
+    GPIO6_30,
 };

 constexpr GPIO gpio[] = {
@@ -372,6 +441,41 @@ constexpr GPIO gpio[] = {
    [GPIO5_15] = {pins[P6_7], 5, 15, 4},
    [GPIO5_16] = {pins[P6_8], 5, 16, 4},
    [GPIO5_18] = {pins[P9_5], 5, 18, 4},
+// PRALINE-specific GPIOs (use placeholder pins on non-PRALINE builds)
+#ifdef PRALINE
+    [GPIO4_14] = {pins[P9_2], 4, 14, 0},   // RFFC5072 mixer data
+    [GPIO4_1] = {pins[P8_1], 4, 1, 0},     // VAA disable
+    [GPIO4_6] = {pins[P8_6], 4, 6, 0},     // LED4
+    [GPIO4_7] = {pins[P8_7], 4, 7, 0},     // 1V2 enable
+    [GPIO4_8] = {pins[PA_1], 4, 8, 0},     // LPF enable
+    [GPIO4_9] = {pins[PA_2], 4, 9, 0},     // RF amp enable
+    [GPIO7_1] = {pins[PE_1], 7, 1, 4},     // MAX2831 enable
+    [GPIO7_2] = {pins[PE_2], 7, 2, 4},     // MAX2831 RX enable
+    [GPIO7_3] = {pins[PE_3], 7, 3, 4},     // P2 port control 0
+    [GPIO7_4] = {pins[PE_4], 7, 4, 4},     // P2 port control 1
+    [GPIO6_25] = {pins[PD_11], 6, 25, 4},  // Mixer lock detect
+    [GPIO6_26] = {pins[PD_12], 6, 26, 4},  // Trigger input
+    [GPIO6_28] = {pins[PD_14], 6, 28, 4},  // MAX283x chip select
+    [GPIO6_29] = {pins[PD_15], 6, 29, 4},  // MAX2831 RXHP
+    [GPIO6_30] = {pins[PD_16], 6, 30, 4},  // MAX5864 chip select
+#else
+    // Placeholder entries for non-PRALINE builds (use P0_0 as dummy)
+    [GPIO4_14] = {pins[P0_0], 4, 14, 0},
+    [GPIO4_1] = {pins[P0_0], 4, 1, 0},
+    [GPIO4_6] = {pins[P0_0], 4, 6, 0},
+    [GPIO4_7] = {pins[P0_0], 4, 7, 0},
+    [GPIO4_8] = {pins[P0_0], 4, 8, 0},
+    [GPIO4_9] = {pins[P0_0], 4, 9, 0},
+    [GPIO7_1] = {pins[P0_0], 7, 1, 0},
+    [GPIO7_2] = {pins[P0_0], 7, 2, 0},
+    [GPIO7_3] = {pins[P0_0], 7, 3, 0},
+    [GPIO7_4] = {pins[P0_0], 7, 4, 0},
+    [GPIO6_25] = {pins[P0_0], 6, 25, 0},
+    [GPIO6_26] = {pins[P0_0], 6, 26, 0},
+    [GPIO6_28] = {pins[P0_0], 6, 28, 0},
+    [GPIO6_29] = {pins[P0_0], 6, 29, 0},
+    [GPIO6_30] = {pins[P0_0], 6, 30, 0},
+#endif
 };

 }  // namespace lpc43xx
@@ -51,6 +51,17 @@ const Config config{block_0, block_1};

 } /* namespace rev_20170522 */

+#ifdef PRALINE
+namespace rev_h4m {
+
+extern const std::array<uint16_t, 3328> block_0;
+extern const std::array<uint16_t, 512> block_1;
+
+const Config config{block_0, block_1};
+
+} /* namespace rev_h4m */
+#endif
+
 } /* namespace cpld */
 } /* namespace portapack */

@@ -85,6 +85,14 @@ struct SharedMemory {
    uint16_t volatile m4_stack_usage{0};
    uint32_t volatile m4_heap_usage{0};
    uint16_t volatile m4_buffer_missed{0};
+
+#ifdef PRALINE
+    // Phase 0 instrumentation counters for PRALINE radio debugging
+    uint32_t volatile m4_dma_xfr_count{0};    // DMA transfer_complete() calls
+    uint32_t volatile m4_dma_wait_count{0};   // wait_for_buffer() calls
+    uint32_t volatile m4_baseband_loops{0};   // Main loop iterations
+    uint8_t volatile m4_streaming_marker{0};  // Proves streaming_enable() called
+#endif
 };

 extern SharedMemory& shared_memory;