HackRF Pro (praline) arch-port initial PR (#2958)

* Initial commit and pr for HackRF Pro (praline) arch-port to mayhem-firmware. Please see https://github.com/portapack-mayhem/mayhem-firmware/issues/2957. Added flash specifics for -DBOARD=PRALINE. This firmware only builds with toolchain v9.2.1 if hackrf codebase has -B arm in firmware/hackrf_usb/CMakeLists.txt. * Updated CMakeLists.txt per coordination with @HtoToo. For -DBOARD=PRALINE FLASH_MB_SIZE and FLASH_MB_LIMIT_SIZE are now 4. Removed praline specific variable for FLASH limits. * Updated chibios-portapack's board.cpp to support initialization of the HachRF-Pro (praline) FPGA. Added append_fpga_bitstream.py tool to ensure that praline_fgpa.bin bitstream can be appended to -DBOARD=PRALINE produced firmware. In order to ensure successful execution of append_fpga_bitstream.py to append the fpga bitstream we should expect that the bistsream will be located at 0x180000 in flash. This requires that FLASH_MB_LIMIT_SIZE must be 1.5, and FLASH_BYTES_LIMIT_SIZE must be 1535 * 1024. If we want to allow more or less space for the base firmware image sans the fpga bitstream the location of the bistream must be moved to a location other than 0x180000. * Updated location of praline_fpga.bin bitstream to 0x380000 to allow more room for firmware. Firmware now has 3.5MB, or 2MB more available than before as coordinated with @HTotoo. * Expanded #ifndef PRALINE to include og and r9 gpio and pin setup as coordinated with @HTotoo. * Added note for PRALINE FLASH_MB_LIMIT_SIZE and FLASH_BYTES_LIMIT_SIZE to explain why we are using the 3.5 and 3584 values respectively as coordinated with @HTotoo. * Next round of modifications derived heavily, if not entirely from work done by @banandana at https://github.com/Banandana/mayhem-firmware. This commit should power on the HackRF Pro (praline) display, power on the fpga, and enable gpio, and provide debug utilties. There is still a lot of work to be done to fully enable the new praline board with this build and firmware architectural porting effort. However, hackrf-one boards do not seem to be adversely impacted by the #ifdef PRALINE statements, and CMakeLists updates, as far as I have been able to test. * Ran format-code.sh. Updates for this commit are only due to formatting. Tested builds and they seem to work as exptected. * Addressed fixes in firmware/application and firmware/baseband. Stream now flows to capture and looking glass. Issues were related to thread management. Issues were originally addressed by @banandana. * Ran format-code.sh to allow for consistency with autoamted clang checks. * Update hackrf ref repo to mayhem-portapack-hackrf next from https://github.com/portapack-mayhem/hackrf * Addressed format edits necessary to pass clang-format check. * Starting addressing Si5351 Clocks for radio sampling. These updates correctly set the Si5351 clock at start up. There appears to be an issue during runtime when testing with RX Test Init, Capture and Looking glass. * Updated clock_manager.cpp to restore correct function introduced by @banandana when testing with Rx Test Init. * Switched to using decimation for setting the sample rate without changing the Si5351 clock. This assumes that for the praline board Si5351 CLK0 runs at fixed 8 MHz (constant) and the FPGA decimates to get the desired sample rate. For example, for a 1 MHz sample rate -> Si5351 outputs 8 MHz, FPGA decimates by 8. There is still more work needed here, and potential verification that this is the correct way to operate with this new archteitecture. * After deliberating on hackrf_usb hackrf_core.c and radio.c, and reviewing firmware/application/hw/si5351.cpp the original approach of using the aproach detailed in hackrf_core.c sample_rate_frac_set() lines 580-582, via the implementation in firmware/application/hw/si5351.cpp seems like the best place to continue testing efforts. * Tested at ~2.4GHz (2.3 - 2.5) with lookgin glass and was able to receive signals. Added a Signal Path debug app to test gains, and readio mode (receive/transmit). * Added two debug apps for the RFFC507x. Status View and Tuning View. This helped debug some of the potential issues with tuning. * update submodule * format code * Small touch up merging latest next and ensuring build for HackRF One. * Reverted edits to re: firmware/baseband/sd_over_usb/scsi.c and firmware/application/portapack.cpp. Source now builds, had to pull latest hackrf submodule. * Skipped detect hardware for praline board to avoid backscreen in HackRF Pro praline board. --------- Co-authored-by: gullradriel <gullradriel@users.noreply.github.com>
2026-08-20 14:39:01 +00:00 · 2026-02-11 03:15:11 -05:00
parent cd30022b61
commit 39424632bb
50 changed files with 4822 additions and 48 deletions
@@ -26,6 +26,14 @@
 #include "rffc507x.hpp"
 #include "max2837.hpp"
 #include "max2839.hpp"
+
+#ifdef PRALINE
+#include "max2831.hpp"
+extern "C" {
+#include "fpga_bridge.h"
+}
+#endif
+
 #include "max5864.hpp"
 #include "baseband_cpld.hpp"

@@ -42,6 +50,10 @@ using namespace hackrf::one;
 #include "portapack.hpp"
 #include "portapack_persistent_memory.hpp"

+#include "hal.h"  // For LPC_SGPIO
+
+#include <array>
+
 /* Direct access to the radio. Setting values incorrectly can damage
 * the device. Applications should use ReceiverModel or TransmitterModel
 * instead of calling these functions directly. */
@@ -56,6 +68,18 @@ static constexpr uint32_t ssp_scr(
    return static_cast<uint8_t>(pclk_f / cpsr / spi_f - 1);
 }

+#ifdef PRALINE
+/* MAX2831 uses 9-bit SPI transfers */
+static constexpr SPIConfig ssp_config_max283x = {
+    .end_cb = NULL,
+    .ssport = gpio_max283x_select.port(),
+    .sspad = gpio_max283x_select.pad(),
+    .cr0 =
+        CR0_CLOCKRATE(ssp_scr(ssp1_pclk_f, ssp1_cpsr, max283x_spi_f) + 3) | CR0_FRFSPI | CR0_DSS9BIT,
+    .cpsr = ssp1_cpsr,
+};
+#else
+/* MAX2837/MAX2839 use 16-bit SPI transfers */
 static constexpr SPIConfig ssp_config_max283x = {
    .end_cb = NULL,
    .ssport = gpio_max283x_select.port(),
@@ -64,6 +88,7 @@ static constexpr SPIConfig ssp_config_max283x = {
        CR0_CLOCKRATE(ssp_scr(ssp1_pclk_f, ssp1_cpsr, max283x_spi_f) + 3) | CR0_FRFSPI | CR0_DSS16BIT,
    .cpsr = ssp1_cpsr,
 };
+#endif

 static constexpr SPIConfig ssp_config_max5864 = {
    .end_cb = NULL,
@@ -89,6 +114,9 @@ rffc507x::RFFC507x first_if;
 max283x::MAX283x* second_if;
 max2837::MAX2837 second_if_max2837{ssp1_target_max283x};
 max2839::MAX2839 second_if_max2839{ssp1_target_max283x};
+#ifdef PRALINE
+max2831::MAX2831 second_if_max2831{ssp1_target_max283x};
+#endif
 static max5864::MAX5864 baseband_codec{ssp1_target_max5864};
 static baseband::CPLD baseband_cpld;

@@ -97,19 +125,46 @@ static rf::Direction direction{rf::Direction::Receive};
 static bool baseband_invert = false;
 static bool mixer_invert = false;

+#ifdef PRALINE
+static rf::Direction cached_direction = rf::Direction::Receive;
+static bool cached_rf_amp = false;
+static int_fast8_t cached_lna_gain = 0;
+static int_fast8_t cached_vga_gain = 0;
+#endif
+
 void init() {
+#ifdef PRALINE
+    /* PRALINE uses MAX2831 transceiver */
+    second_if = (max283x::MAX283x*)&second_if_max2831;
+#else
    if (hackrf_r9) {
        gpio_r9_not_ant_pwr.write(1);
        gpio_r9_not_ant_pwr.output();
    }
-    rf_path.init();
-    first_if.init();
    second_if = hackrf_r9
                    ? (max283x::MAX283x*)&second_if_max2839
                    : (max283x::MAX283x*)&second_if_max2837;
+#endif
+    rf_path.init();
+    first_if.init();
    second_if->init();
    baseband_codec.init();
+#ifndef PRALINE
+    /* HackRF One uses CPLD for Q inversion control.
+     * PRALINE uses FPGA and the pin (P2_3) is used for LCD_TE on H4M. */
    baseband_cpld.init();
+#else
+    /* Initialize FPGA registers - DC_BLOCK must be enabled for RX */
+    // debug::fpga::init();
+    fpga_debug_register_write(1, 0x01);  // DC_BLOCK=1, QUARTER_SHIFT=0, Q_INVERT=0
+    fpga_debug_register_write(2, 0x00);  // RX_DECIM=0 (no decimation for testing)
+    fpga_debug_register_write(3, 0x00);  // TX_CTRL=0
+    fpga_debug_register_write(4, 0x00);  // TX_INTRP=0
+    fpga_debug_register_write(5, 0x00);  // TX_PSTEP=0
+
+    ssp1_arbiter.invalidate();
+    chThdSleepMilliseconds(10);  // Let FPGA registers settle
+#endif
 }

 void set_direction(const rf::Direction new_direction) {
@@ -120,6 +175,10 @@ void set_direction(const rf::Direction new_direction) {
    // Deleting that load_sram_no_verify() (or the original , load_sram() ), solves random TX swap I/Q  problem in H1R1 , others OK- (and no side effects to all).
    // hackrf::cpld::load_sram_no_verify();  // After commit "removed the use of the hackrf cpld eeprom #1732", in a H1R1,  Mic App wrong SSB TX with random USB/LSB change.

+#ifdef PRALINE
+    cached_direction = new_direction;  // Track state for debug and potentially other purposes.
+#endif
+
    direction = new_direction;

    if (hackrf_r9) {
@@ -143,7 +202,18 @@ void set_direction(const rf::Direction new_direction) {
         */
        baseband_invert = false;
    }
+#ifndef PRALINE
    baseband_cpld.set_invert(mixer_invert ^ baseband_invert);
+#else
+    // Praline: Control Q inversion via FPGA register
+    // Assuming register 1 bit 1 controls Q inversion
+    uint8_t ctrl_reg = 0x01;  // DC_BLOCK enabled
+    if (mixer_invert ^ baseband_invert) {
+        ctrl_reg |= 0x02;  // Set Q_INVERT bit
+    }
+    fpga_debug_register_write(1, ctrl_reg);
+    ssp1_arbiter.invalidate();
+#endif

    second_if->set_mode((direction == rf::Direction::Transmit) ? max283x::Mode::Transmit : max283x::Mode::Receive);
    rf_path.set_direction(direction);
@@ -154,6 +224,16 @@ void set_direction(const rf::Direction new_direction) {
        led_rx.on();
    else
        led_tx.on();
+
+    // #ifdef PRALINE
+    //  Try with Q inversion OFF
+    // fpga_debug_register_write(1, 0x01);  // DC_BLOCK=1, Q_INVERT=0
+    // ssp1_arbiter.invalidate();
+
+    // If no signals, try with Q inversion ON
+    // fpga_debug_register_write(1, 0x03);  // DC_BLOCK=1, Q_INVERT=1
+    // ssp1_arbiter.invalidate();
+    // #endif
 }

 bool set_tuning_frequency(const rf::Frequency frequency) {
@@ -196,7 +276,9 @@ bool set_tuning_frequency(const rf::Frequency frequency) {

        rf_path.set_band(tuning_config.rf_path_band);
        mixer_invert = tuning_config.mixer_invert;
+#ifndef PRALINE
        baseband_cpld.set_invert(mixer_invert ^ baseband_invert);
+#endif

        return result_second_if;
    } else {
@@ -205,14 +287,23 @@ bool set_tuning_frequency(const rf::Frequency frequency) {
 }

 void set_rf_amp(const bool rf_amp) {
+#ifdef PRALINE
+    cached_rf_amp = rf_amp;  // Track state for debug and potentialy other purposes.
+#endif
    rf_path.set_rf_amp(rf_amp);
 }

 void set_lna_gain(const int_fast8_t db) {
+#ifdef PRALINE
+    cached_lna_gain = db;  // Track state for debug and potentially other purposes.
+#endif
    second_if->set_lna_gain(db);
 }

 void set_vga_gain(const int_fast8_t db) {
+#ifdef PRALINE
+    cached_vga_gain = db;  // Track state for debug and potentially other purposes.
+#endif
    second_if->set_vga_gain(db);
 }

@@ -235,11 +326,17 @@ void set_baseband_rate(const uint32_t rate) {

 void set_antenna_bias(const bool on) {
    /* Pull MOSFET gate low to turn on antenna bias. */
+#ifdef PRALINE
+    // Praline: P2_12 = GPIO1[12], ANT_BIAS_EN_N (active LOW)
+    LPC_GPIO->CLR[1] = on ? (1 << 12) : 0;
+    LPC_GPIO->SET[1] = on ? 0 : (1 << 12);
+#else
    if (hackrf_r9) {
        gpio_r9_not_ant_pwr.write(on ? 0 : 1);
    } else {
        first_if.set_gpo1(on ? 0 : 1);
    }
+#endif
 }

 void set_tx_max283x_iq_phase_calibration(const size_t v) {
@@ -275,8 +372,32 @@ void disable() {
    led_tx.off();
 }

+#ifdef PRALINE
+void invalidate_spi_config() {
+    ssp1_arbiter.invalidate();
+}
+#endif
+
 namespace debug {

+#ifdef PRALINE
+rf::Direction get_cached_direction() {
+    return cached_direction;
+}
+
+bool get_cached_rf_amp() {
+    return cached_rf_amp;
+}
+
+int_fast8_t get_cached_lna_gain() {
+    return cached_lna_gain;
+}
+
+int_fast8_t get_cached_vga_gain() {
+    return cached_vga_gain;
+}
+#endif
+
 namespace first_if {

 uint32_t register_read(const size_t register_number) {
@@ -287,6 +408,48 @@ void register_write(const size_t register_number, uint32_t value) {
    radio::first_if.write(register_number, value);
 }

+#ifdef PRALINE
+extern "C" {
+extern struct rffc507x_debug_t {
+    uint32_t requested_freq_mhz;
+    uint32_t calculated_vco_mhz;
+    uint32_t expected_n;
+    uint8_t expected_lodiv;
+    uint8_t expected_presc;
+    bool was_called;
+    uint32_t calc_lo_freq_mhz;
+    uint32_t calc_vco_inside_mhz;
+    uint8_t calc_lodiv_log2;
+    uint8_t calc_presc_log2;
+    uint64_t calc_n_q24;
+} rffc507x_debug_info;
+}
+
+/*struct TuningInfo {
+    uint32_t requested_freq_mhz;
+    uint32_t expected_n;
+    uint8_t expected_lodiv;
+    uint8_t expected_presc;
+    bool was_called;
+};*/
+
+TuningInfo get_tuning_info() {
+    return {
+        rffc507x_debug_info.requested_freq_mhz,
+        rffc507x_debug_info.calculated_vco_mhz,
+        rffc507x_debug_info.expected_n,
+        rffc507x_debug_info.expected_lodiv,
+        rffc507x_debug_info.expected_presc,
+        rffc507x_debug_info.was_called,
+        rffc507x_debug_info.calc_lo_freq_mhz,
+        rffc507x_debug_info.calc_vco_inside_mhz,
+        rffc507x_debug_info.calc_lodiv_log2,
+        rffc507x_debug_info.calc_presc_log2,
+        rffc507x_debug_info.calc_n_q24,
+    };
+}
+#endif
+
 } /* namespace first_if */

 namespace second_if {
@@ -305,6 +468,73 @@ int8_t temp_sense() {

 } /* namespace second_if */

+#ifdef PRALINE
+namespace fpga {
+
+/* Use fpga_bridge.c functions for FPGA register access.
+ * These properly switch SPI mode between iCE40 (Mode 3, 8-bit)
+ * and MAX2831 (Mode 0, 9-bit). After each access, we must
+ * invalidate the SPI arbiter's cached config since fpga_bridge.c
+ * modifies SSP1 registers directly. */
+
+uint32_t register_read(const size_t register_number) {
+    uint32_t result = fpga_debug_register_read(static_cast<uint8_t>(register_number));
+    ssp1_arbiter.invalidate();  // Force arbiter to reconfigure on next transfer
+    return result;
+}
+
+void register_write(const size_t register_number, uint32_t value) {
+    fpga_debug_register_write(static_cast<uint8_t>(register_number), static_cast<uint8_t>(value));
+    ssp1_arbiter.invalidate();  // Force arbiter to reconfigure on next transfer
+}
+
+void init() {
+    // Initialize FPGA registers after bitstream load
+    // DC_BLOCK (bit 0) must be enabled for RX to work
+    fpga_debug_register_write(1, 0x01);  // CTRL: DC_BLOCK=1
+    fpga_debug_register_write(2, 0x00);  // RX_DECIM: no decimation
+    fpga_debug_register_write(3, 0x00);  // TX_CTRL: NCO disabled
+    fpga_debug_register_write(4, 0x00);  // TX_INTRP: no interpolation
+    fpga_debug_register_write(5, 0x00);  // TX_PSTEP: zero phase step
+    ssp1_arbiter.invalidate();           // Force arbiter to reconfigure on next transfer
+}
+
+} /* namespace fpga */
+#endif
+
+namespace sgpio {
+
+/* SGPIO register map for debug viewing
+ * We expose key registers for diagnosing data flow issues.
+ * Register numbers map to:
+ * 0: CTRL_ENABLE   - Which slices are enabled
+ * 1: GPIO_INREG    - GPIO input register (data pins state)
+ * 2: GPIO_OUTREG   - GPIO output register (direction, disable, etc)
+ * 3: GPIO_OENREG   - GPIO output enable register
+ * 4: STATUS_1      - Exchange interrupt status (slice A = bit 0)
+ * 5: REG_SS[0]     - Shadow register slice A (current sample data)
+ */
+uint32_t register_read(const size_t register_number) {
+    switch (register_number) {
+        case 0:
+            return LPC_SGPIO->CTRL_ENABLE;
+        case 1:
+            return LPC_SGPIO->GPIO_INREG;
+        case 2:
+            return LPC_SGPIO->GPIO_OUTREG;
+        case 3:
+            return LPC_SGPIO->GPIO_OENREG;
+        case 4:
+            return LPC_SGPIO->STATUS_1;
+        case 5:
+            return LPC_SGPIO->REG_SS[0];
+        default:
+            return 0xFFFFFFFF;
+    }
+}
+
+} /* namespace sgpio */
+
 } /* namespace debug */

 } /* namespace radio */