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HackRF Pro (praline) arch-port initial PR (#2958)
* Initial commit and pr for HackRF Pro (praline) arch-port to mayhem-firmware. Please see https://github.com/portapack-mayhem/mayhem-firmware/issues/2957. Added flash specifics for -DBOARD=PRALINE. This firmware only builds with toolchain v9.2.1 if hackrf codebase has -B arm in firmware/hackrf_usb/CMakeLists.txt. * Updated CMakeLists.txt per coordination with @HtoToo. For -DBOARD=PRALINE FLASH_MB_SIZE and FLASH_MB_LIMIT_SIZE are now 4. Removed praline specific variable for FLASH limits. * Updated chibios-portapack's board.cpp to support initialization of the HachRF-Pro (praline) FPGA. Added append_fpga_bitstream.py tool to ensure that praline_fgpa.bin bitstream can be appended to -DBOARD=PRALINE produced firmware. In order to ensure successful execution of append_fpga_bitstream.py to append the fpga bitstream we should expect that the bistsream will be located at 0x180000 in flash. This requires that FLASH_MB_LIMIT_SIZE must be 1.5, and FLASH_BYTES_LIMIT_SIZE must be 1535 * 1024. If we want to allow more or less space for the base firmware image sans the fpga bitstream the location of the bistream must be moved to a location other than 0x180000. * Updated location of praline_fpga.bin bitstream to 0x380000 to allow more room for firmware. Firmware now has 3.5MB, or 2MB more available than before as coordinated with @HTotoo. * Expanded #ifndef PRALINE to include og and r9 gpio and pin setup as coordinated with @HTotoo. * Added note for PRALINE FLASH_MB_LIMIT_SIZE and FLASH_BYTES_LIMIT_SIZE to explain why we are using the 3.5 and 3584 values respectively as coordinated with @HTotoo. * Next round of modifications derived heavily, if not entirely from work done by @banandana at https://github.com/Banandana/mayhem-firmware. This commit should power on the HackRF Pro (praline) display, power on the fpga, and enable gpio, and provide debug utilties. There is still a lot of work to be done to fully enable the new praline board with this build and firmware architectural porting effort. However, hackrf-one boards do not seem to be adversely impacted by the #ifdef PRALINE statements, and CMakeLists updates, as far as I have been able to test. * Ran format-code.sh. Updates for this commit are only due to formatting. Tested builds and they seem to work as exptected. * Addressed fixes in firmware/application and firmware/baseband. Stream now flows to capture and looking glass. Issues were related to thread management. Issues were originally addressed by @banandana. * Ran format-code.sh to allow for consistency with autoamted clang checks. * Update hackrf ref repo to mayhem-portapack-hackrf next from https://github.com/portapack-mayhem/hackrf * Addressed format edits necessary to pass clang-format check. * Starting addressing Si5351 Clocks for radio sampling. These updates correctly set the Si5351 clock at start up. There appears to be an issue during runtime when testing with RX Test Init, Capture and Looking glass. * Updated clock_manager.cpp to restore correct function introduced by @banandana when testing with Rx Test Init. * Switched to using decimation for setting the sample rate without changing the Si5351 clock. This assumes that for the praline board Si5351 CLK0 runs at fixed 8 MHz (constant) and the FPGA decimates to get the desired sample rate. For example, for a 1 MHz sample rate -> Si5351 outputs 8 MHz, FPGA decimates by 8. There is still more work needed here, and potential verification that this is the correct way to operate with this new archteitecture. * After deliberating on hackrf_usb hackrf_core.c and radio.c, and reviewing firmware/application/hw/si5351.cpp the original approach of using the aproach detailed in hackrf_core.c sample_rate_frac_set() lines 580-582, via the implementation in firmware/application/hw/si5351.cpp seems like the best place to continue testing efforts. * Tested at ~2.4GHz (2.3 - 2.5) with lookgin glass and was able to receive signals. Added a Signal Path debug app to test gains, and readio mode (receive/transmit). * Added two debug apps for the RFFC507x. Status View and Tuning View. This helped debug some of the potential issues with tuning. * update submodule * format code * Small touch up merging latest next and ensuring build for HackRF One. * Reverted edits to re: firmware/baseband/sd_over_usb/scsi.c and firmware/application/portapack.cpp. Source now builds, had to pull latest hackrf submodule. * Skipped detect hardware for praline board to avoid backscreen in HackRF Pro praline board. --------- Co-authored-by: gullradriel <gullradriel@users.noreply.github.com>
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@@ -31,6 +31,24 @@ using namespace hackrf::one;
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#include "hal.h"
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#ifdef PRALINE
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// Global debug tracking - visible to other files
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struct rffc507x_debug_t {
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uint32_t requested_freq_mhz;
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uint32_t calculated_vco_mhz;
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uint32_t expected_n;
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uint8_t expected_lodiv;
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uint8_t expected_presc;
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bool was_called;
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uint32_t calc_lo_freq_mhz; // Input to calculate()
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uint32_t calc_vco_inside_mhz; // VCO calculated inside calculate()
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uint8_t calc_lodiv_log2; // LO divider log2
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uint8_t calc_presc_log2; // Prescaler log2
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uint64_t calc_n_q24; // N in Q24 format before shift
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};
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rffc507x_debug_t rffc507x_debug_info = {0, 0, 0, 0, 0, false, 0, 0, 0, 0, 0};
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#endif
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namespace rffc507x {
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/* Empirical tests indicate no minimum reset pulse width, but the speed
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@@ -96,9 +114,31 @@ constexpr size_t divider_min = 1U << divider_log2_min;
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constexpr size_t divider_max = 1U << divider_log2_max;
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constexpr size_t divider_log2(const rf::Frequency vco_frequency) {
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#ifdef PRALINE
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// PRALINE FIX: Avoid N register overflow (9-bit max = 511)
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// With 40 MHz reference:
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// - For VCO=5400 MHz, presc=÷2: N = (5400×2)/40 = 270 ✓
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// - For VCO=5400 MHz, presc=÷4: N = (5400×4)/40 = 540 ✗ OVERFLOW!
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//
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// Maximum safe VCO for ÷4 prescaler:
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// N_max = 511, so VCO_max = (511 × 40) / 4 = 5110 MHz
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//
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// Use ÷4 only if VCO < 5110 MHz AND VCO > 3200 MHz
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// Use ÷2 for VCO >= 5110 MHz to avoid overflow
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constexpr rf::Frequency overflow_threshold = 5110000000ULL; // Max VCO for ÷4
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constexpr rf::Frequency min_presc4_freq = 3200000000ULL; // Min VCO for ÷4
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if ((vco_frequency > min_presc4_freq) && (vco_frequency < overflow_threshold)) {
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return divider_log2_max; // ÷4 prescaler
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} else {
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return divider_log2_min; // ÷2 prescaler
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}
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#else
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return (vco_frequency > (prescaler::divider_min * prescaler::max_frequency))
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? prescaler::divider_log2_max
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: prescaler::divider_log2_min;
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#endif
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}
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} /* namespace prescaler */
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@@ -121,9 +161,22 @@ struct SynthConfig {
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const size_t prescaler_divider_log2 = prescaler::divider_log2(vco_frequency);
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#ifndef PRALINE
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const uint64_t prescaled_lo_q24 = vco_frequency << (24 - prescaler_divider_log2);
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#else
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const uint64_t prescaled_lo_q24 = vco_frequency << (24 + prescaler_divider_log2);
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#endif
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const uint64_t n_divider_q24 = prescaled_lo_q24 / reference_frequency;
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#ifdef PRALINE
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// DEBUG: Track everything
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rffc507x_debug_info.calc_lo_freq_mhz = lo_frequency / 1000000;
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rffc507x_debug_info.calc_vco_inside_mhz = vco_frequency / 1000000;
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rffc507x_debug_info.calc_lodiv_log2 = lo_divider_log2;
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rffc507x_debug_info.calc_presc_log2 = prescaler_divider_log2;
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rffc507x_debug_info.calc_n_q24 = n_divider_q24;
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#endif
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return {
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lo_divider_log2,
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prescaler_divider_log2,
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@@ -233,6 +286,20 @@ void RFFC507x::set_mixer_current(const uint8_t value) {
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void RFFC507x::set_frequency(const rf::Frequency lo_frequency) {
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const SynthConfig synth_config = SynthConfig::calculate(lo_frequency);
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#ifdef PRALINE
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// Calculate VCO frequency from LO frequency and divider
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const size_t lo_divider = 1U << synth_config.lo_divider_log2; // 2^lodiv_log2
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const rf::Frequency vco_freq = lo_frequency * lo_divider;
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// Track what we calculated
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rffc507x_debug_info.requested_freq_mhz = lo_frequency / 1000000;
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rffc507x_debug_info.calculated_vco_mhz = vco_freq / 1000000;
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rffc507x_debug_info.expected_n = synth_config.n_divider_q24 >> 24;
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rffc507x_debug_info.expected_lodiv = synth_config.lo_divider_log2;
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rffc507x_debug_info.expected_presc = synth_config.prescaler_divider_log2;
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rffc507x_debug_info.was_called = true;
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#endif
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/* Boost charge pump leakage if VCO frequency > 3.2GHz, indicated by
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* prescaler divider set to 4 (log2=2) instead of 2 (log2=1).
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*/
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