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https://github.com/portapack-mayhem/mayhem-firmware.git
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HackRF Pro (praline) arch-port initial PR (#2958)
* Initial commit and pr for HackRF Pro (praline) arch-port to mayhem-firmware. Please see https://github.com/portapack-mayhem/mayhem-firmware/issues/2957. Added flash specifics for -DBOARD=PRALINE. This firmware only builds with toolchain v9.2.1 if hackrf codebase has -B arm in firmware/hackrf_usb/CMakeLists.txt. * Updated CMakeLists.txt per coordination with @HtoToo. For -DBOARD=PRALINE FLASH_MB_SIZE and FLASH_MB_LIMIT_SIZE are now 4. Removed praline specific variable for FLASH limits. * Updated chibios-portapack's board.cpp to support initialization of the HachRF-Pro (praline) FPGA. Added append_fpga_bitstream.py tool to ensure that praline_fgpa.bin bitstream can be appended to -DBOARD=PRALINE produced firmware. In order to ensure successful execution of append_fpga_bitstream.py to append the fpga bitstream we should expect that the bistsream will be located at 0x180000 in flash. This requires that FLASH_MB_LIMIT_SIZE must be 1.5, and FLASH_BYTES_LIMIT_SIZE must be 1535 * 1024. If we want to allow more or less space for the base firmware image sans the fpga bitstream the location of the bistream must be moved to a location other than 0x180000. * Updated location of praline_fpga.bin bitstream to 0x380000 to allow more room for firmware. Firmware now has 3.5MB, or 2MB more available than before as coordinated with @HTotoo. * Expanded #ifndef PRALINE to include og and r9 gpio and pin setup as coordinated with @HTotoo. * Added note for PRALINE FLASH_MB_LIMIT_SIZE and FLASH_BYTES_LIMIT_SIZE to explain why we are using the 3.5 and 3584 values respectively as coordinated with @HTotoo. * Next round of modifications derived heavily, if not entirely from work done by @banandana at https://github.com/Banandana/mayhem-firmware. This commit should power on the HackRF Pro (praline) display, power on the fpga, and enable gpio, and provide debug utilties. There is still a lot of work to be done to fully enable the new praline board with this build and firmware architectural porting effort. However, hackrf-one boards do not seem to be adversely impacted by the #ifdef PRALINE statements, and CMakeLists updates, as far as I have been able to test. * Ran format-code.sh. Updates for this commit are only due to formatting. Tested builds and they seem to work as exptected. * Addressed fixes in firmware/application and firmware/baseband. Stream now flows to capture and looking glass. Issues were related to thread management. Issues were originally addressed by @banandana. * Ran format-code.sh to allow for consistency with autoamted clang checks. * Update hackrf ref repo to mayhem-portapack-hackrf next from https://github.com/portapack-mayhem/hackrf * Addressed format edits necessary to pass clang-format check. * Starting addressing Si5351 Clocks for radio sampling. These updates correctly set the Si5351 clock at start up. There appears to be an issue during runtime when testing with RX Test Init, Capture and Looking glass. * Updated clock_manager.cpp to restore correct function introduced by @banandana when testing with Rx Test Init. * Switched to using decimation for setting the sample rate without changing the Si5351 clock. This assumes that for the praline board Si5351 CLK0 runs at fixed 8 MHz (constant) and the FPGA decimates to get the desired sample rate. For example, for a 1 MHz sample rate -> Si5351 outputs 8 MHz, FPGA decimates by 8. There is still more work needed here, and potential verification that this is the correct way to operate with this new archteitecture. * After deliberating on hackrf_usb hackrf_core.c and radio.c, and reviewing firmware/application/hw/si5351.cpp the original approach of using the aproach detailed in hackrf_core.c sample_rate_frac_set() lines 580-582, via the implementation in firmware/application/hw/si5351.cpp seems like the best place to continue testing efforts. * Tested at ~2.4GHz (2.3 - 2.5) with lookgin glass and was able to receive signals. Added a Signal Path debug app to test gains, and readio mode (receive/transmit). * Added two debug apps for the RFFC507x. Status View and Tuning View. This helped debug some of the potential issues with tuning. * update submodule * format code * Small touch up merging latest next and ensuring build for HackRF One. * Reverted edits to re: firmware/baseband/sd_over_usb/scsi.c and firmware/application/portapack.cpp. Source now builds, had to pull latest hackrf submodule. * Skipped detect hardware for praline board to avoid backscreen in HackRF Pro praline board. --------- Co-authored-by: gullradriel <gullradriel@users.noreply.github.com>
This commit is contained in:
stafur
GitHub
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/*
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* Copyright (C) 2025 Great Scott Gadgets
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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/*
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* MAX2831 driver ported from GSG HackRF reference implementation (max2831.c).
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* Adapted to work with Mayhem's MAX283x abstraction layer.
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*/
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#ifdef PRALINE
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#include "max2831.hpp"
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#include "hackrf_hal.hpp"
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#include "hackrf_gpio.hpp"
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using namespace hackrf::one;
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#include "ch.h"
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#include "hal.h"
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#include <algorithm>
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#include <cstring>
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namespace max2831 {
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using namespace max283x;
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/*
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* MAX2831 uses 9-bit SPI transfers.
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* An 18-bit word is sent as two 9-bit transfers:
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* Word format: [VALUE:14][REG:4]
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* First transfer: bits 17:9 (high 9 bits)
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* Second transfer: bits 8:0 (low 9 bits)
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*
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* This matches the GSG reference implementation exactly.
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*/
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void MAX2831::write_reg(const uint8_t reg, const uint16_t value) {
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uint32_t word = (((uint32_t)value & 0x3fff) << 4) | (reg & 0xf);
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uint16_t values[2] = {
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static_cast<uint16_t>(word >> 9),
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static_cast<uint16_t>(word & 0x1ff)};
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_target.transfer(values, 2);
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}
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void MAX2831::set_reg_field(const uint8_t reg, const uint16_t mask, const uint16_t value) {
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_regs[reg] = (_regs[reg] & ~mask) | (value & mask);
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mark_dirty(reg);
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}
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uint16_t MAX2831::get_reg_field(const uint8_t reg, const uint16_t mask, const uint8_t shift) {
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return (_regs[reg] & mask) >> shift;
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}
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void MAX2831::mark_dirty(const uint8_t reg) {
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_regs_dirty |= (1 << reg);
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}
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void MAX2831::mark_clean(const uint8_t reg) {
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_regs_dirty &= ~(1 << reg);
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}
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void MAX2831::flush_reg(const uint8_t reg) {
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write_reg(reg, _regs[reg]);
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mark_clean(reg);
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}
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void MAX2831::flush_dirty() {
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for (size_t r = 0; r < reg_count; r++) {
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if ((_regs_dirty >> r) & 0x1) {
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flush_reg(r);
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}
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}
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}
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void MAX2831::init() {
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set_mode(Mode::Shutdown);
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/* Configure GPIO pins for MAX2831 control */
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gpio_max283x_enable.output();
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gpio_max2831_rx_enable.output();
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gpio_max2831_rxhp.output();
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gpio_max2831_rxhp.write(0); /* RXHP low = 100 Hz HPF (default) */
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/* Reset to default register values */
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std::memcpy(_regs.data(), default_regs.data(), sizeof(_regs));
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_regs_dirty = 0xFFFF;
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/* Write default register values to chip */
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flush_dirty();
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/* Use SPI control instead of B1-B7 pins for gain settings.
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* This matches the GSG reference: max2831_setup() */
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set_reg_field(8, REG8_RXVGA_GAIN_SPI_EN, REG8_RXVGA_GAIN_SPI_EN);
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set_reg_field(9, REG9_TXVGA_GAIN_SPI_EN, REG9_TXVGA_GAIN_SPI_EN);
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/* Set initial gains - matches GSG reference */
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set_reg_field(12, REG12_TXVGA_GAIN_MASK, 0x00); /* Minimum TX gain */
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set_reg_field(7, REG7_RX_HPF_SEL_MASK, REG7_RX_HPF_30KHZ);
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set_reg_field(11, REG11_LNA_GAIN_MASK, REG11_LNA_GAIN_MAX);
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set_reg_field(11, REG11_RXVGA_GAIN_MASK, 0x18); // Moderate RX VGA gain
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/* FORCE MAXIMUM GAIN FOR TESTING */
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// set_reg_field(11, REG11_RXVGA_GAIN_MASK, 0x1F); // 62 dB VGA = MAX
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/* Configure baseband filter for 8 MHz TX - matches GSG reference */
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set_reg_field(8, REG8_LPF_COARSE_MASK, REG8_RX_LPF_7_5M);
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set_reg_field(7, REG7_RX_LPF_FINE_MASK, REG7_RX_LPF_FINE_100);
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set_reg_field(7, REG7_TX_LPF_FINE_MASK, REG7_TX_LPF_FINE_100);
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/* Disable clock output */
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set_reg_field(14, REG14_CLKOUT_PIN_EN, 0);
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/* Write all modified registers */
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flush_dirty();
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set_mode(Mode::Standby);
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}
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void MAX2831::set_mode(const Mode mode) {
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_mode = mode;
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/*
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* MAX2831 mode control via ENABLE and RXTX pins.
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* From GSG hackrf max2831_target.c:
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*
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* Shutdown: ENABLE=0, RXTX=0
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* Standby: ENABLE=0, RXTX=1 (PLL/VCO/LO on, ready for quick TX/RX)
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* RX: ENABLE=1, RXTX=0
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* TX: ENABLE=1, RXTX=1
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*
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* Note: gpio_max2831_rx_enable is the RXTX mode select pin.
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* RXTX=0 selects RX, RXTX=1 selects TX.
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*/
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/* Handle calibration mode bits if needed */
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bool tx_cal = (mode == Mode::Tx_Calibration);
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bool rx_cal = (mode == Mode::Rx_Calibration);
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uint16_t current_tx_cal = get_reg_field(6, REG6_TX_CAL_MODE_EN, REG6_TX_CAL_MODE_EN_SHIFT);
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uint16_t current_rx_cal = get_reg_field(6, REG6_RX_CAL_MODE_EN, REG6_RX_CAL_MODE_EN_SHIFT);
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if (current_tx_cal != (tx_cal ? 1 : 0)) {
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set_reg_field(6, REG6_TX_CAL_MODE_EN, tx_cal ? REG6_TX_CAL_MODE_EN : 0);
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flush_dirty();
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}
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if (current_rx_cal != (rx_cal ? 1 : 0)) {
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set_reg_field(6, REG6_RX_CAL_MODE_EN, rx_cal ? REG6_RX_CAL_MODE_EN : 0);
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flush_dirty();
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}
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switch (mode) {
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default:
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case Mode::Shutdown:
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gpio_max2831_rx_enable.write(0); /* RXTX=0 */
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gpio_max283x_enable.write(0); /* ENABLE=0 */
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break;
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case Mode::Standby:
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gpio_max2831_rx_enable.write(1); /* RXTX=1 */
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gpio_max283x_enable.write(0); /* ENABLE=0 */
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break;
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case Mode::Transmit:
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case Mode::Tx_Calibration:
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gpio_max2831_rx_enable.write(1); /* RXTX=1 for TX */
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gpio_max283x_enable.write(1); /* ENABLE=1 */
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break;
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case Mode::Receive:
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case Mode::Rx_Calibration:
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gpio_max2831_rx_enable.write(0); /* RXTX=0 for RX */
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gpio_max283x_enable.write(1); /* ENABLE=1 */
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break;
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}
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/* Update LPF bandwidth for current mode */
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if (_desired_lpf_bw > 0) {
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set_lpf_bandwidth_internal(_desired_lpf_bw);
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}
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}
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void MAX2831::set_tx_vga_gain(const int_fast8_t db) {
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/* TX VGA gain: 0-31 dB in ~1 dB steps
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* Register value: gain * 2 | 1, max 0x3F
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* This matches GSG reference: max2831_set_txvga_gain() */
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int_fast8_t db_clipped = std::max(0, std::min(31, (int)db));
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uint16_t value = std::min((db_clipped << 1) | 1, 0x3f);
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set_reg_field(12, REG12_TXVGA_GAIN_MASK, value);
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flush_reg(12);
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}
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void MAX2831::set_lna_gain(const int_fast8_t db) {
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/*
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* LNA gain has 3 settings (from GSG reference):
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* MAX (33 dB), -16 dB from max (17 dB), -33 dB from max (0 dB)
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* Map from MAX2837 8 dB steps for compatibility
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*/
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uint16_t gain_val;
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if (db >= 32) {
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gain_val = REG11_LNA_GAIN_MAX;
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} else if (db >= 16) {
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gain_val = REG11_LNA_GAIN_M16;
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} else {
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gain_val = REG11_LNA_GAIN_M33;
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}
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set_reg_field(11, REG11_LNA_GAIN_MASK, gain_val);
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flush_reg(11);
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}
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void MAX2831::set_vga_gain(const int_fast8_t db) {
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/* VGA gain: 0-62 dB in 2 dB steps
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* This matches GSG reference: max2831_set_vga_gain() */
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if ((db & 0x1) || db > 62) {
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return; /* Invalid: must be even and <= 62 */
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}
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int_fast8_t db_clipped = std::max(0, std::min(62, (int)db));
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uint16_t value = (db_clipped >> 1) & 0x1f;
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set_reg_field(11, REG11_RXVGA_GAIN_MASK, value);
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flush_reg(11);
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}
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/*
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* LPF bandwidth tables from GSG reference max2831.c
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*/
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struct lpf_ft_t {
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uint32_t bandwidth_hz;
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uint8_t ft;
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};
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struct lpf_ft_fine_t {
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uint8_t percent;
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uint8_t ft_fine;
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};
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/* Measured -0.5 dB complex baseband bandwidth for each register setting */
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static constexpr lpf_ft_t rx_lpf_ft[] = {
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{11600000, REG8_RX_LPF_7_5M},
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{15100000, REG8_RX_LPF_8_5M},
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{22600000, REG8_RX_LPF_15M},
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{28300000, REG8_RX_LPF_18M},
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{0, 0},
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};
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static constexpr lpf_ft_fine_t rx_lpf_ft_fine[] = {
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{90, REG7_RX_LPF_FINE_90},
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{95, REG7_RX_LPF_FINE_95},
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{100, REG7_RX_LPF_FINE_100},
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{105, REG7_RX_LPF_FINE_105},
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{110, REG7_RX_LPF_FINE_110},
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{0, 0},
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};
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static constexpr lpf_ft_t tx_lpf_ft[] = {
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{11900000, REG8_TX_LPF_8M},
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{15800000, REG8_TX_LPF_11M},
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{23600000, REG8_TX_LPF_16_5M},
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{31300000, REG8_TX_LPF_22_5M},
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{0, 0},
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};
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static constexpr lpf_ft_fine_t tx_lpf_ft_fine[] = {
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{90, REG7_TX_LPF_FINE_90},
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{95, REG7_TX_LPF_FINE_95},
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{100, REG7_TX_LPF_FINE_100},
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{105, REG7_TX_LPF_FINE_105},
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{110, REG7_TX_LPF_FINE_110},
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{115, REG7_TX_LPF_FINE_115},
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{0, 0},
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};
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uint32_t MAX2831::set_lpf_bandwidth_internal(const uint32_t bandwidth_hz) {
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const lpf_ft_t* coarse;
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const lpf_ft_fine_t* fine;
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if (_mode == Mode::Receive || _mode == Mode::Rx_Calibration) {
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coarse = rx_lpf_ft;
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fine = rx_lpf_ft_fine;
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} else {
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coarse = tx_lpf_ft;
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fine = tx_lpf_ft_fine;
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}
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/* Find coarse and fine settings for LPF - matches GSG reference */
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bool found = false;
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const lpf_ft_fine_t* f = fine;
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for (; coarse->bandwidth_hz != 0; coarse++) {
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uint32_t coarse_aux = coarse->bandwidth_hz / 100;
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for (f = fine; f->percent != 0; f++) {
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if ((coarse_aux * f->percent) >= bandwidth_hz) {
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found = true;
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break;
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}
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}
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if (found) break;
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}
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/* Use the widest setting if a wider bandwidth than our maximum is requested */
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if (!found) {
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coarse--;
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f--;
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}
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/* Program found settings */
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set_reg_field(8, REG8_LPF_COARSE_MASK, coarse->ft);
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if (_mode == Mode::Receive || _mode == Mode::Rx_Calibration) {
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set_reg_field(7, REG7_RX_LPF_FINE_MASK, f->ft_fine);
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} else {
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/* TX fine values are already shifted in the constants (REG7_TX_LPF_FINE_*) */
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set_reg_field(7, REG7_TX_LPF_FINE_MASK, f->ft_fine);
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}
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flush_dirty();
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return coarse->bandwidth_hz * f->percent / 100;
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}
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void MAX2831::set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum) {
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_desired_lpf_bw = bandwidth_minimum;
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if (_mode == Mode::Receive || _mode == Mode::Rx_Calibration) {
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set_lpf_bandwidth_internal(bandwidth_minimum);
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}
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}
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void MAX2831::set_lpf_rf_bandwidth_tx(const uint32_t bandwidth_minimum) {
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_desired_lpf_bw = bandwidth_minimum;
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if (_mode == Mode::Transmit || _mode == Mode::Tx_Calibration) {
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set_lpf_bandwidth_internal(bandwidth_minimum);
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}
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}
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bool MAX2831::set_frequency(const rf::Frequency lo_frequency) {
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/*
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* MAX2831 frequency synthesis from GSG reference max2831_set_frequency():
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* F_LO = F_REF * (N + F/2^20) / R
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* Where:
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* F_REF = 40 MHz reference
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* R = reference divider (1 or 2), we use R=2
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* N = integer divider (8 bits)
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* F = fractional divider (20 bits)
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*
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* Using R=2: F_LO = 40M * (N + F/2^20) / 2 = 20M * (N + F/2^20)
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*/
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/* MAX2831 supports 2.3-2.6 GHz */
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if (lo_frequency < 2300000000ULL || lo_frequency > 2600000000ULL) {
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return false;
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}
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||||
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/* From GSG reference: ASSUME 40MHz PLL. Ratio = F*R/40,000,000.
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* TODO: fixed to R=2. Check if it's worth exploring R=1. */
|
||||
uint32_t freq = lo_frequency;
|
||||
freq += (20000000 >> 21); /* Round to nearest frequency */
|
||||
uint32_t div_int = freq / 20000000;
|
||||
uint32_t div_rem = freq % 20000000;
|
||||
uint32_t div_frac = 0;
|
||||
uint32_t div_cmp = 20000000;
|
||||
|
||||
for (int i = 0; i < 20; i++) {
|
||||
div_frac <<= 1;
|
||||
div_rem <<= 1;
|
||||
if (div_rem >= div_cmp) {
|
||||
div_frac |= 0x1;
|
||||
div_rem -= div_cmp;
|
||||
}
|
||||
}
|
||||
|
||||
/* Write order matters - matches GSG reference */
|
||||
/* REG 3: SYN_INT (bits 7:0) and SYN_FRAC_LO (bits 13:8) */
|
||||
uint16_t reg3_val = (div_int & 0xFF) | ((div_frac & 0x3F) << 8);
|
||||
_regs[3] = reg3_val;
|
||||
mark_dirty(3);
|
||||
|
||||
/* REG 4: SYN_FRAC_HI (bits 13:0) - upper 14 bits of 20-bit fractional */
|
||||
uint16_t reg4_val = (div_frac >> 6) & 0x3FFF;
|
||||
_regs[4] = reg4_val;
|
||||
mark_dirty(4);
|
||||
|
||||
flush_dirty();
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void MAX2831::set_rx_LO_iq_phase_calibration(const size_t v) {
|
||||
/* MAX2831 doesn't have the same IQ calibration as MAX2837 */
|
||||
(void)v;
|
||||
}
|
||||
|
||||
void MAX2831::set_tx_LO_iq_phase_calibration(const size_t v) {
|
||||
/* MAX2831 doesn't have the same IQ calibration as MAX2837 */
|
||||
(void)v;
|
||||
}
|
||||
|
||||
void MAX2831::set_rx_buff_vcm(const size_t v) {
|
||||
/* MAX2831 RX IQ common mode voltage is in register 15
|
||||
* Values: 0=1.1V, 1=1.2V, 2=1.3V, 3=1.45V */
|
||||
uint16_t vcm = std::min(v, (size_t)3) << REG15_RXIQ_VCM_SHIFT;
|
||||
set_reg_field(15, REG15_RXIQ_VCM_MASK, vcm);
|
||||
flush_reg(15);
|
||||
}
|
||||
|
||||
int8_t MAX2831::temp_sense() {
|
||||
/* MAX2831 temperature sensor can be read via RSSI MUX.
|
||||
* This would require:
|
||||
* 1. Switch RSSI_MUX to temperature mode
|
||||
* 2. Read the ADC
|
||||
* 3. Switch back to RSSI mode
|
||||
* For now, return a placeholder value. */
|
||||
return 25; /* Room temperature placeholder */
|
||||
}
|
||||
|
||||
reg_t MAX2831::read(const address_t reg_num) {
|
||||
/* MAX2831 doesn't support SPI read, return cached value */
|
||||
if (reg_num < reg_count) {
|
||||
return _regs[reg_num];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void MAX2831::write(const address_t reg_num, const reg_t value) {
|
||||
if (reg_num < reg_count) {
|
||||
_regs[reg_num] = value & 0x3FFF; /* 14-bit registers */
|
||||
write_reg(reg_num, _regs[reg_num]);
|
||||
mark_clean(reg_num);
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace max2831
|
||||
#endif
|
||||
@@ -0,0 +1,220 @@
|
||||
/*
|
||||
* Copyright (C) 2025 Great Scott Gadgets
|
||||
*
|
||||
* This file is part of PortaPack.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 51 Franklin Street,
|
||||
* Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
/*
|
||||
* MAX2831 driver ported from GSG HackRF reference implementation.
|
||||
* Register definitions match max2831_regs.def from hackrf firmware.
|
||||
*/
|
||||
|
||||
#ifndef __MAX2831_H__
|
||||
#define __MAX2831_H__
|
||||
|
||||
#include "max283x.hpp"
|
||||
#include "gpio.hpp"
|
||||
#include "spi_arbiter.hpp"
|
||||
|
||||
#include <cstdint>
|
||||
#include <array>
|
||||
|
||||
namespace max2831 {
|
||||
|
||||
using namespace max283x;
|
||||
|
||||
/* MAX2831 has 16 registers, each containing 14 bits of data */
|
||||
constexpr size_t reg_count = 16;
|
||||
|
||||
/* Default register values from GSG HackRF reference (max2831.c) */
|
||||
constexpr std::array<uint16_t, reg_count> default_regs = {
|
||||
0x1740, /* 0: enable fractional mode (Table 16 recommends 0x0740, clearing unknown bit) */
|
||||
0x119a, /* 1 */
|
||||
0x1003, /* 2 */
|
||||
0x0079, /* 3: PLL divider settings for 2437 MHz */
|
||||
0x3666, /* 4: PLL divider settings for 2437 MHz */
|
||||
0x00a4, /* 5: divide reference frequency by 2 */
|
||||
0x0060, /* 6: enable TX power detector */
|
||||
0x1022, /* 7: 110% TX LPF bandwidth */
|
||||
0x2021, /* 8: pin control of RX gain, 11 MHz LPF bandwidth */
|
||||
0x03b5, /* 9: pin control of TX gain */
|
||||
0x1d80, /* 10: 3.5 us PA enable delay, zero PA bias */
|
||||
0x0074, /* 11: LNA high gain, RX VGA moderate gain (Table 27 recommends 0x007f, maximum gain) */
|
||||
0x0140, /* 12: TX VGA minimum */
|
||||
0x0e92, /* 13 */
|
||||
0x0100, /* 14: reference clock output disabled */
|
||||
0x0145, /* 15: RX IQ common mode 1.1 V */
|
||||
};
|
||||
|
||||
/*
|
||||
* Register bit field definitions from max2831_regs.def
|
||||
* Format: REG<num>_<field>_<info>
|
||||
*/
|
||||
|
||||
/* REG 0: PLL Mode */
|
||||
constexpr uint16_t REG0_PLL_MODE_SHIFT = 10;
|
||||
constexpr uint16_t REG0_PLL_MODE_MASK = (1 << REG0_PLL_MODE_SHIFT);
|
||||
constexpr uint16_t REG0_PLL_MODE_INTEGER = 0;
|
||||
constexpr uint16_t REG0_PLL_MODE_FRACTIONAL = 1;
|
||||
|
||||
/* REG 3: Synthesizer Integer and Fractional Low */
|
||||
constexpr uint16_t REG3_SYN_INT_SHIFT = 0;
|
||||
constexpr uint16_t REG3_SYN_INT_MASK = 0x00FF; /* D7:D0 - Integer divider (8 bits) */
|
||||
constexpr uint16_t REG3_SYN_FRAC_LO_SHIFT = 8;
|
||||
constexpr uint16_t REG3_SYN_FRAC_LO_MASK = 0x3F00; /* D13:D8 - Low 6 bits of fractional divider */
|
||||
|
||||
/* REG 4: Synthesizer Fractional High */
|
||||
constexpr uint16_t REG4_SYN_FRAC_HI_MASK = 0x3FFF; /* D13:D0 - High 14 bits of fractional divider */
|
||||
|
||||
/* REG 5: Reference Divider and Lock Detect */
|
||||
constexpr uint16_t REG5_SYN_REF_DIV_SHIFT = 2;
|
||||
constexpr uint16_t REG5_SYN_REF_DIV_1 = (0 << REG5_SYN_REF_DIV_SHIFT);
|
||||
constexpr uint16_t REG5_SYN_REF_DIV_2 = (1 << REG5_SYN_REF_DIV_SHIFT);
|
||||
|
||||
/* REG 6: Calibration Mode */
|
||||
constexpr uint16_t REG6_RX_CAL_MODE_EN_SHIFT = 0;
|
||||
constexpr uint16_t REG6_RX_CAL_MODE_EN = (1 << REG6_RX_CAL_MODE_EN_SHIFT);
|
||||
constexpr uint16_t REG6_TX_CAL_MODE_EN_SHIFT = 1;
|
||||
constexpr uint16_t REG6_TX_CAL_MODE_EN = (1 << REG6_TX_CAL_MODE_EN_SHIFT);
|
||||
constexpr uint16_t REG6_TX_POWER_DETECT_EN_SHIFT = 6;
|
||||
constexpr uint16_t REG6_TX_POWER_DETECT_EN = (1 << REG6_TX_POWER_DETECT_EN_SHIFT);
|
||||
|
||||
/* REG 7: LPF Fine Adjustment and RX HPF */
|
||||
constexpr uint16_t REG7_RX_LPF_FINE_SHIFT = 0;
|
||||
constexpr uint16_t REG7_RX_LPF_FINE_MASK = 0x0007; /* D2:D0 */
|
||||
constexpr uint16_t REG7_RX_LPF_FINE_90 = 0;
|
||||
constexpr uint16_t REG7_RX_LPF_FINE_95 = 1;
|
||||
constexpr uint16_t REG7_RX_LPF_FINE_100 = 2;
|
||||
constexpr uint16_t REG7_RX_LPF_FINE_105 = 3;
|
||||
constexpr uint16_t REG7_RX_LPF_FINE_110 = 4;
|
||||
|
||||
constexpr uint16_t REG7_TX_LPF_FINE_SHIFT = 3;
|
||||
constexpr uint16_t REG7_TX_LPF_FINE_MASK = 0x0038; /* D5:D3 */
|
||||
constexpr uint16_t REG7_TX_LPF_FINE_90 = (0 << REG7_TX_LPF_FINE_SHIFT);
|
||||
constexpr uint16_t REG7_TX_LPF_FINE_95 = (1 << REG7_TX_LPF_FINE_SHIFT);
|
||||
constexpr uint16_t REG7_TX_LPF_FINE_100 = (2 << REG7_TX_LPF_FINE_SHIFT);
|
||||
constexpr uint16_t REG7_TX_LPF_FINE_105 = (3 << REG7_TX_LPF_FINE_SHIFT);
|
||||
constexpr uint16_t REG7_TX_LPF_FINE_110 = (4 << REG7_TX_LPF_FINE_SHIFT);
|
||||
constexpr uint16_t REG7_TX_LPF_FINE_115 = (5 << REG7_TX_LPF_FINE_SHIFT);
|
||||
|
||||
constexpr uint16_t REG7_RX_HPF_SEL_SHIFT = 12;
|
||||
constexpr uint16_t REG7_RX_HPF_SEL_MASK = 0x3000; /* D13:D12 */
|
||||
constexpr uint16_t REG7_RX_HPF_100HZ = (0 << REG7_RX_HPF_SEL_SHIFT);
|
||||
constexpr uint16_t REG7_RX_HPF_4KHZ = (1 << REG7_RX_HPF_SEL_SHIFT);
|
||||
constexpr uint16_t REG7_RX_HPF_30KHZ = (2 << REG7_RX_HPF_SEL_SHIFT);
|
||||
|
||||
/* REG 8: LPF Coarse, RSSI MUX, and RX VGA SPI Enable */
|
||||
constexpr uint16_t REG8_LPF_COARSE_SHIFT = 0;
|
||||
constexpr uint16_t REG8_LPF_COARSE_MASK = 0x0003; /* D1:D0 */
|
||||
/* RX and TX share the same coarse LPF setting bits */
|
||||
constexpr uint16_t REG8_RX_LPF_7_5M = 0;
|
||||
constexpr uint16_t REG8_RX_LPF_8_5M = 1;
|
||||
constexpr uint16_t REG8_RX_LPF_15M = 2;
|
||||
constexpr uint16_t REG8_RX_LPF_18M = 3;
|
||||
constexpr uint16_t REG8_TX_LPF_8M = 0;
|
||||
constexpr uint16_t REG8_TX_LPF_11M = 1;
|
||||
constexpr uint16_t REG8_TX_LPF_16_5M = 2;
|
||||
constexpr uint16_t REG8_TX_LPF_22_5M = 3;
|
||||
|
||||
constexpr uint16_t REG8_RSSI_MUX_SHIFT = 8;
|
||||
constexpr uint16_t REG8_RSSI_MUX_MASK = 0x0300; /* D9:D8 */
|
||||
constexpr uint16_t REG8_RSSI_MUX_RSSI = (0 << REG8_RSSI_MUX_SHIFT);
|
||||
constexpr uint16_t REG8_RSSI_MUX_TEMP = (1 << REG8_RSSI_MUX_SHIFT);
|
||||
constexpr uint16_t REG8_RSSI_MUX_TX_POWER = (2 << REG8_RSSI_MUX_SHIFT);
|
||||
|
||||
constexpr uint16_t REG8_RXVGA_GAIN_SPI_EN_SHIFT = 12;
|
||||
constexpr uint16_t REG8_RXVGA_GAIN_SPI_EN = (1 << REG8_RXVGA_GAIN_SPI_EN_SHIFT);
|
||||
|
||||
/* REG 9: TX VGA SPI Enable */
|
||||
constexpr uint16_t REG9_TXVGA_GAIN_SPI_EN_SHIFT = 10;
|
||||
constexpr uint16_t REG9_TXVGA_GAIN_SPI_EN = (1 << REG9_TXVGA_GAIN_SPI_EN_SHIFT);
|
||||
|
||||
/* REG 11: RX Gain */
|
||||
constexpr uint16_t REG11_RXVGA_GAIN_SHIFT = 0;
|
||||
constexpr uint16_t REG11_RXVGA_GAIN_MASK = 0x001F; /* D4:D0 - 5 bits */
|
||||
|
||||
constexpr uint16_t REG11_LNA_GAIN_SHIFT = 5;
|
||||
constexpr uint16_t REG11_LNA_GAIN_MASK = 0x0060; /* D6:D5 - 2 bits */
|
||||
constexpr uint16_t REG11_LNA_GAIN_M33 = (0 << REG11_LNA_GAIN_SHIFT); /* -33 dB from max (min) */
|
||||
constexpr uint16_t REG11_LNA_GAIN_M16 = (2 << REG11_LNA_GAIN_SHIFT); /* -16 dB from max */
|
||||
constexpr uint16_t REG11_LNA_GAIN_MAX = (3 << REG11_LNA_GAIN_SHIFT); /* Maximum LNA gain */
|
||||
|
||||
/* REG 12: TX VGA Gain */
|
||||
constexpr uint16_t REG12_TXVGA_GAIN_SHIFT = 0;
|
||||
constexpr uint16_t REG12_TXVGA_GAIN_MASK = 0x003F; /* D5:D0 - 6 bits */
|
||||
|
||||
/* REG 14: Clock Output */
|
||||
constexpr uint16_t REG14_CLKOUT_PIN_EN_SHIFT = 9;
|
||||
constexpr uint16_t REG14_CLKOUT_PIN_EN = (1 << REG14_CLKOUT_PIN_EN_SHIFT);
|
||||
|
||||
/* REG 15: RX IQ Common Mode */
|
||||
constexpr uint16_t REG15_RXIQ_VCM_SHIFT = 10;
|
||||
constexpr uint16_t REG15_RXIQ_VCM_MASK = 0x0C00; /* D11:D10 - 2 bits */
|
||||
constexpr uint16_t REG15_RXIQ_VCM_1_1 = (0 << REG15_RXIQ_VCM_SHIFT); /* 1.1V */
|
||||
constexpr uint16_t REG15_RXIQ_VCM_1_2 = (1 << REG15_RXIQ_VCM_SHIFT); /* 1.2V */
|
||||
constexpr uint16_t REG15_RXIQ_VCM_1_3 = (2 << REG15_RXIQ_VCM_SHIFT); /* 1.3V */
|
||||
constexpr uint16_t REG15_RXIQ_VCM_1_45 = (3 << REG15_RXIQ_VCM_SHIFT); /* 1.45V */
|
||||
|
||||
class MAX2831 : public MAX283x {
|
||||
public:
|
||||
constexpr MAX2831(
|
||||
spi::arbiter::Target& target)
|
||||
: _target(target) {
|
||||
}
|
||||
|
||||
void init() override;
|
||||
void set_mode(const Mode mode) override;
|
||||
|
||||
void set_tx_vga_gain(const int_fast8_t db) override;
|
||||
void set_lna_gain(const int_fast8_t db) override;
|
||||
void set_vga_gain(const int_fast8_t db) override;
|
||||
void set_lpf_rf_bandwidth_rx(const uint32_t bandwidth_minimum) override;
|
||||
void set_lpf_rf_bandwidth_tx(const uint32_t bandwidth_minimum) override;
|
||||
|
||||
bool set_frequency(const rf::Frequency lo_frequency) override;
|
||||
|
||||
void set_rx_LO_iq_phase_calibration(const size_t v) override;
|
||||
void set_tx_LO_iq_phase_calibration(const size_t v) override;
|
||||
|
||||
void set_rx_buff_vcm(const size_t v) override;
|
||||
|
||||
int8_t temp_sense() override;
|
||||
|
||||
reg_t read(const address_t reg_num) override;
|
||||
void write(const address_t reg_num, const reg_t value) override;
|
||||
|
||||
private:
|
||||
spi::arbiter::Target& _target;
|
||||
Mode _mode{Mode::Standby};
|
||||
std::array<uint16_t, reg_count> _regs{default_regs};
|
||||
uint16_t _regs_dirty{0xFFFF}; /* Track which registers need to be written */
|
||||
uint32_t _desired_lpf_bw{0}; /* Desired LPF bandwidth in Hz */
|
||||
|
||||
void write_reg(const uint8_t reg, const uint16_t value);
|
||||
void set_reg_field(const uint8_t reg, const uint16_t mask, const uint16_t value);
|
||||
uint16_t get_reg_field(const uint8_t reg, const uint16_t mask, const uint8_t shift);
|
||||
void mark_dirty(const uint8_t reg);
|
||||
void mark_clean(const uint8_t reg);
|
||||
void flush_reg(const uint8_t reg);
|
||||
void flush_dirty();
|
||||
uint32_t set_lpf_bandwidth_internal(const uint32_t bandwidth_hz);
|
||||
};
|
||||
|
||||
} // namespace max2831
|
||||
|
||||
#endif /*__MAX2831_H__*/
|
||||
@@ -31,6 +31,24 @@ using namespace hackrf::one;
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
#ifdef PRALINE
|
||||
// Global debug tracking - visible to other files
|
||||
struct rffc507x_debug_t {
|
||||
uint32_t requested_freq_mhz;
|
||||
uint32_t calculated_vco_mhz;
|
||||
uint32_t expected_n;
|
||||
uint8_t expected_lodiv;
|
||||
uint8_t expected_presc;
|
||||
bool was_called;
|
||||
uint32_t calc_lo_freq_mhz; // Input to calculate()
|
||||
uint32_t calc_vco_inside_mhz; // VCO calculated inside calculate()
|
||||
uint8_t calc_lodiv_log2; // LO divider log2
|
||||
uint8_t calc_presc_log2; // Prescaler log2
|
||||
uint64_t calc_n_q24; // N in Q24 format before shift
|
||||
};
|
||||
rffc507x_debug_t rffc507x_debug_info = {0, 0, 0, 0, 0, false, 0, 0, 0, 0, 0};
|
||||
#endif
|
||||
|
||||
namespace rffc507x {
|
||||
|
||||
/* Empirical tests indicate no minimum reset pulse width, but the speed
|
||||
@@ -96,9 +114,31 @@ constexpr size_t divider_min = 1U << divider_log2_min;
|
||||
constexpr size_t divider_max = 1U << divider_log2_max;
|
||||
|
||||
constexpr size_t divider_log2(const rf::Frequency vco_frequency) {
|
||||
#ifdef PRALINE
|
||||
// PRALINE FIX: Avoid N register overflow (9-bit max = 511)
|
||||
// With 40 MHz reference:
|
||||
// - For VCO=5400 MHz, presc=÷2: N = (5400×2)/40 = 270 ✓
|
||||
// - For VCO=5400 MHz, presc=÷4: N = (5400×4)/40 = 540 ✗ OVERFLOW!
|
||||
//
|
||||
// Maximum safe VCO for ÷4 prescaler:
|
||||
// N_max = 511, so VCO_max = (511 × 40) / 4 = 5110 MHz
|
||||
//
|
||||
// Use ÷4 only if VCO < 5110 MHz AND VCO > 3200 MHz
|
||||
// Use ÷2 for VCO >= 5110 MHz to avoid overflow
|
||||
|
||||
constexpr rf::Frequency overflow_threshold = 5110000000ULL; // Max VCO for ÷4
|
||||
constexpr rf::Frequency min_presc4_freq = 3200000000ULL; // Min VCO for ÷4
|
||||
|
||||
if ((vco_frequency > min_presc4_freq) && (vco_frequency < overflow_threshold)) {
|
||||
return divider_log2_max; // ÷4 prescaler
|
||||
} else {
|
||||
return divider_log2_min; // ÷2 prescaler
|
||||
}
|
||||
#else
|
||||
return (vco_frequency > (prescaler::divider_min * prescaler::max_frequency))
|
||||
? prescaler::divider_log2_max
|
||||
: prescaler::divider_log2_min;
|
||||
#endif
|
||||
}
|
||||
|
||||
} /* namespace prescaler */
|
||||
@@ -121,9 +161,22 @@ struct SynthConfig {
|
||||
|
||||
const size_t prescaler_divider_log2 = prescaler::divider_log2(vco_frequency);
|
||||
|
||||
#ifndef PRALINE
|
||||
const uint64_t prescaled_lo_q24 = vco_frequency << (24 - prescaler_divider_log2);
|
||||
#else
|
||||
const uint64_t prescaled_lo_q24 = vco_frequency << (24 + prescaler_divider_log2);
|
||||
#endif
|
||||
const uint64_t n_divider_q24 = prescaled_lo_q24 / reference_frequency;
|
||||
|
||||
#ifdef PRALINE
|
||||
// DEBUG: Track everything
|
||||
rffc507x_debug_info.calc_lo_freq_mhz = lo_frequency / 1000000;
|
||||
rffc507x_debug_info.calc_vco_inside_mhz = vco_frequency / 1000000;
|
||||
rffc507x_debug_info.calc_lodiv_log2 = lo_divider_log2;
|
||||
rffc507x_debug_info.calc_presc_log2 = prescaler_divider_log2;
|
||||
rffc507x_debug_info.calc_n_q24 = n_divider_q24;
|
||||
#endif
|
||||
|
||||
return {
|
||||
lo_divider_log2,
|
||||
prescaler_divider_log2,
|
||||
@@ -233,6 +286,20 @@ void RFFC507x::set_mixer_current(const uint8_t value) {
|
||||
void RFFC507x::set_frequency(const rf::Frequency lo_frequency) {
|
||||
const SynthConfig synth_config = SynthConfig::calculate(lo_frequency);
|
||||
|
||||
#ifdef PRALINE
|
||||
// Calculate VCO frequency from LO frequency and divider
|
||||
const size_t lo_divider = 1U << synth_config.lo_divider_log2; // 2^lodiv_log2
|
||||
const rf::Frequency vco_freq = lo_frequency * lo_divider;
|
||||
|
||||
// Track what we calculated
|
||||
rffc507x_debug_info.requested_freq_mhz = lo_frequency / 1000000;
|
||||
rffc507x_debug_info.calculated_vco_mhz = vco_freq / 1000000;
|
||||
rffc507x_debug_info.expected_n = synth_config.n_divider_q24 >> 24;
|
||||
rffc507x_debug_info.expected_lodiv = synth_config.lo_divider_log2;
|
||||
rffc507x_debug_info.expected_presc = synth_config.prescaler_divider_log2;
|
||||
rffc507x_debug_info.was_called = true;
|
||||
#endif
|
||||
|
||||
/* Boost charge pump leakage if VCO frequency > 3.2GHz, indicated by
|
||||
* prescaler divider set to 4 (log2=2) instead of 2 (log2=1).
|
||||
*/
|
||||
|
||||
@@ -57,7 +57,15 @@ void Si5351::reset() {
|
||||
write_register(Register::CrystalInternalLoadCapacitance, 0b11010010);
|
||||
write_register(Register::FanoutEnable, 0x00);
|
||||
|
||||
#ifndef PRALINE
|
||||
reset_plls();
|
||||
#endif
|
||||
// NOTE: Do NOT call reset_plls() here!
|
||||
// Multisynth registers are not yet configured at this point.
|
||||
// Resetting PLLs with power-on default multisynth values (divider=6)
|
||||
// causes Si5351 to output wrong frequencies (66.666 MHz instead of 8 MHz).
|
||||
// The PLL reset should happen in init_clock_generator() AFTER multisynths
|
||||
// are properly configured. This matches HackRF reference firmware.
|
||||
}
|
||||
|
||||
Si5351::regvalue_t Si5351::read_register(const uint8_t reg) {
|
||||
@@ -93,7 +101,16 @@ void Si5351::set_ms_frequency(
|
||||
.r_div = r_div,
|
||||
};
|
||||
const auto regs = ms.reg(ms_number);
|
||||
|
||||
#ifdef PRALINE
|
||||
/* PRALINE: Use single-byte writes - multi-byte I2C writes seem to fail */
|
||||
const uint8_t base_reg = regs[0];
|
||||
for (size_t i = 1; i < regs.size(); i++) {
|
||||
write_register(base_reg + i - 1, regs[i]);
|
||||
}
|
||||
#else
|
||||
write(regs);
|
||||
#endif
|
||||
}
|
||||
|
||||
} /* namespace si5351 */
|
||||
|
||||
@@ -361,7 +361,16 @@ class Si5351 {
|
||||
}
|
||||
|
||||
void wait_for_device_ready() {
|
||||
#ifndef PRALINE
|
||||
while (device_status() & 0x80);
|
||||
#else
|
||||
// Add timeout to prevent infinite loop if I2C communication fails
|
||||
// (e.g., on PRALINE hardware with different configuration)
|
||||
uint32_t timeout = 100000;
|
||||
while ((device_status() & 0x80) && (timeout > 0)) {
|
||||
timeout--;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
bool plla_loss_of_signal() {
|
||||
@@ -377,10 +386,15 @@ class Si5351 {
|
||||
}
|
||||
|
||||
void reset_plls() {
|
||||
#ifndef PRALINE
|
||||
// Datasheet recommends value 0xac, though the low nibble bits are not defined in AN619.
|
||||
write_register(Register::PLLReset, 0xac);
|
||||
#else
|
||||
// Reset both PLLA and PLLB. Use 0xA0 to match HackRF reference firmware.
|
||||
// The low nibble bits are reserved/undefined in AN619.
|
||||
write_register(Register::PLLReset, 0xa0);
|
||||
#endif
|
||||
}
|
||||
|
||||
regvalue_t read_register(const uint8_t reg);
|
||||
|
||||
template <size_t N>
|
||||
@@ -397,6 +411,18 @@ class Si5351 {
|
||||
write(config.reg(ms_number));
|
||||
}
|
||||
|
||||
#ifdef PRALINE
|
||||
/* Write multisynth config using single-byte writes for debugging */
|
||||
void write_ms_single_byte(const size_t ms_number, const MultisynthFractional& config) {
|
||||
const auto regs = config.reg(ms_number);
|
||||
// regs[0] is the base register address, regs[1-8] are the data bytes
|
||||
const uint8_t base_reg = regs[0];
|
||||
for (size_t i = 1; i < regs.size(); i++) {
|
||||
write_register(base_reg + i - 1, regs[i]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void set_ms_frequency(
|
||||
const size_t ms_number,
|
||||
const uint32_t frequency,
|
||||
@@ -480,7 +506,6 @@ class Si5351 {
|
||||
}});
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace si5351
|
||||
|
||||
#endif /*__SI5351_H__*/
|
||||
|
||||
@@ -46,6 +46,14 @@ class Arbiter {
|
||||
_bus.transfer(data, count);
|
||||
}
|
||||
|
||||
#ifdef PRALINE
|
||||
/* Invalidate cached config - forces reconfiguration on next transfer.
|
||||
* Call this after directly manipulating SSP registers (e.g., FPGA access). */
|
||||
void invalidate() {
|
||||
_config = nullptr;
|
||||
}
|
||||
#endif
|
||||
|
||||
private:
|
||||
SPI& _bus;
|
||||
const SPIConfig* _config;
|
||||
|
||||
Reference in New Issue
Block a user