mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-08-16 12:53:25 +00:00
HackRF Pro (praline) arch-port initial PR (#2958)
* Initial commit and pr for HackRF Pro (praline) arch-port to mayhem-firmware. Please see https://github.com/portapack-mayhem/mayhem-firmware/issues/2957. Added flash specifics for -DBOARD=PRALINE. This firmware only builds with toolchain v9.2.1 if hackrf codebase has -B arm in firmware/hackrf_usb/CMakeLists.txt. * Updated CMakeLists.txt per coordination with @HtoToo. For -DBOARD=PRALINE FLASH_MB_SIZE and FLASH_MB_LIMIT_SIZE are now 4. Removed praline specific variable for FLASH limits. * Updated chibios-portapack's board.cpp to support initialization of the HachRF-Pro (praline) FPGA. Added append_fpga_bitstream.py tool to ensure that praline_fgpa.bin bitstream can be appended to -DBOARD=PRALINE produced firmware. In order to ensure successful execution of append_fpga_bitstream.py to append the fpga bitstream we should expect that the bistsream will be located at 0x180000 in flash. This requires that FLASH_MB_LIMIT_SIZE must be 1.5, and FLASH_BYTES_LIMIT_SIZE must be 1535 * 1024. If we want to allow more or less space for the base firmware image sans the fpga bitstream the location of the bistream must be moved to a location other than 0x180000. * Updated location of praline_fpga.bin bitstream to 0x380000 to allow more room for firmware. Firmware now has 3.5MB, or 2MB more available than before as coordinated with @HTotoo. * Expanded #ifndef PRALINE to include og and r9 gpio and pin setup as coordinated with @HTotoo. * Added note for PRALINE FLASH_MB_LIMIT_SIZE and FLASH_BYTES_LIMIT_SIZE to explain why we are using the 3.5 and 3584 values respectively as coordinated with @HTotoo. * Next round of modifications derived heavily, if not entirely from work done by @banandana at https://github.com/Banandana/mayhem-firmware. This commit should power on the HackRF Pro (praline) display, power on the fpga, and enable gpio, and provide debug utilties. There is still a lot of work to be done to fully enable the new praline board with this build and firmware architectural porting effort. However, hackrf-one boards do not seem to be adversely impacted by the #ifdef PRALINE statements, and CMakeLists updates, as far as I have been able to test. * Ran format-code.sh. Updates for this commit are only due to formatting. Tested builds and they seem to work as exptected. * Addressed fixes in firmware/application and firmware/baseband. Stream now flows to capture and looking glass. Issues were related to thread management. Issues were originally addressed by @banandana. * Ran format-code.sh to allow for consistency with autoamted clang checks. * Update hackrf ref repo to mayhem-portapack-hackrf next from https://github.com/portapack-mayhem/hackrf * Addressed format edits necessary to pass clang-format check. * Starting addressing Si5351 Clocks for radio sampling. These updates correctly set the Si5351 clock at start up. There appears to be an issue during runtime when testing with RX Test Init, Capture and Looking glass. * Updated clock_manager.cpp to restore correct function introduced by @banandana when testing with Rx Test Init. * Switched to using decimation for setting the sample rate without changing the Si5351 clock. This assumes that for the praline board Si5351 CLK0 runs at fixed 8 MHz (constant) and the FPGA decimates to get the desired sample rate. For example, for a 1 MHz sample rate -> Si5351 outputs 8 MHz, FPGA decimates by 8. There is still more work needed here, and potential verification that this is the correct way to operate with this new archteitecture. * After deliberating on hackrf_usb hackrf_core.c and radio.c, and reviewing firmware/application/hw/si5351.cpp the original approach of using the aproach detailed in hackrf_core.c sample_rate_frac_set() lines 580-582, via the implementation in firmware/application/hw/si5351.cpp seems like the best place to continue testing efforts. * Tested at ~2.4GHz (2.3 - 2.5) with lookgin glass and was able to receive signals. Added a Signal Path debug app to test gains, and readio mode (receive/transmit). * Added two debug apps for the RFFC507x. Status View and Tuning View. This helped debug some of the potential issues with tuning. * update submodule * format code * Small touch up merging latest next and ensuring build for HackRF One. * Reverted edits to re: firmware/baseband/sd_over_usb/scsi.c and firmware/application/portapack.cpp. Source now builds, had to pull latest hackrf submodule. * Skipped detect hardware for praline board to avoid backscreen in HackRF Pro praline board. --------- Co-authored-by: gullradriel <gullradriel@users.noreply.github.com>
This commit is contained in:
stafur
GitHub
@@ -23,6 +23,7 @@
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#include "portapack_persistent_memory.hpp"
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#include "portapack_io.hpp"
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#include "portapack.hpp"
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#include "hackrf_hal.hpp"
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using namespace hackrf::one;
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@@ -30,6 +31,14 @@ using namespace hackrf::one;
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#include "lpc43xx_cpp.hpp"
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using namespace lpc43xx;
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#ifdef PRALINE
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extern "C" {
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#include "fpga_bridge.h"
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}
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// Need access to ssp1_arbiter from radio namespace
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#include "radio.hpp"
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#endif
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constexpr uint32_t si5351_vco_f = 800000000;
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constexpr si5351::Inputs si5351_inputs{
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@@ -54,6 +63,12 @@ constexpr si5351::PLL si5351_pll_xtal_25m{
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.c = 1,
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};
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constexpr auto si5351_pll_a_xtal_reg = si5351_pll_xtal_25m.reg(0);
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#ifdef PRALINE
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static_assert(si5351_pll_xtal_25m.f_vco() == si5351_vco_f, "PLL XTAL frequency wrong");
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static_assert(si5351_pll_xtal_25m.p1() == 3584, "PLL XTAL P1 wrong");
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static_assert(si5351_pll_xtal_25m.p2() == 0, "PLL XTAL P2 wrong");
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static_assert(si5351_pll_xtal_25m.p3() == 1, "PLL XTAL P3 wrong");
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#endif
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constexpr si5351::PLL si5351_pll_clkin_10m{
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.f_in = si5351_inputs.f_clkin_out(),
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@@ -64,10 +79,12 @@ constexpr si5351::PLL si5351_pll_clkin_10m{
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constexpr auto si5351c_pll_b_clkin_reg = si5351_pll_clkin_10m.reg(1);
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constexpr auto si5351a_pll_a_clkin_reg = si5351_pll_clkin_10m.reg(0);
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#ifndef PRALINE
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static_assert(si5351_pll_xtal_25m.f_vco() == si5351_vco_f, "PLL XTAL frequency wrong");
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static_assert(si5351_pll_xtal_25m.p1() == 3584, "PLL XTAL P1 wrong");
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static_assert(si5351_pll_xtal_25m.p2() == 0, "PLL XTAL P2 wrong");
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static_assert(si5351_pll_xtal_25m.p3() == 1, "PLL XTAL P3 wrong");
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#endif
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static_assert(si5351_pll_clkin_10m.f_vco() == si5351_vco_f, "PLL CLKIN frequency wrong");
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static_assert(si5351_pll_clkin_10m.p1() == 9728, "PLL CLKIN P1 wrong");
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@@ -101,6 +118,22 @@ constexpr si5351::MultisynthFractional si5351_ms_0_8m{
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};
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constexpr auto si5351c_ms_0_8m_reg = si5351_ms_0_8m.reg(clock_generator_output_og_codec);
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#ifdef PRALINE
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// Verify compile-time values for 8 MHz config
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static_assert(si5351_ms_0_8m.p1() == 5888, "MS0 8MHz P1 should be 5888 (0x1700)");
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static_assert(si5351_ms_0_8m.p2() == 0, "MS0 8MHz P2 should be 0");
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static_assert(si5351_ms_0_8m.p3() == 1, "MS0 8MHz P3 should be 1");
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static_assert(si5351_ms_0_8m.f_out() == 8000000, "MS0 should output 8 MHz");
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// Verify register array encoding
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static_assert(si5351c_ms_0_8m_reg[0] == 42, "MS0 base register should be 42");
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static_assert(si5351c_ms_0_8m_reg[1] == 0x00, "MS0 reg43 P3[15:8] should be 0x00");
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static_assert(si5351c_ms_0_8m_reg[2] == 0x01, "MS0 reg44 P3[7:0] should be 0x01");
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static_assert(si5351c_ms_0_8m_reg[3] == 0x10, "MS0 reg45 R_DIV should be 0x10");
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static_assert(si5351c_ms_0_8m_reg[4] == 0x17, "MS0 reg46 P1[15:8] should be 0x17");
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static_assert(si5351c_ms_0_8m_reg[5] == 0x00, "MS0 reg47 P1[7:0] should be 0x00");
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#endif
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constexpr si5351::MultisynthFractional si5351_ms_group{
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.f_src = si5351_vco_f,
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.a = 80, /* Don't care */
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@@ -204,7 +237,11 @@ constexpr ClockControls si5351c_clock_control_common{{
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}};
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constexpr ClockControls si5351a_clock_control_common{{
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#ifndef PRALINE
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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#else
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{ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off}, // CLK0: MUST be Fractional for 8 MHz!
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#endif
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{ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off},
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{ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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{ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off},
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@@ -255,9 +292,48 @@ static void portapack_tcxo_disable() {
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using namespace hackrf::one;
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void ClockManager::init_clock_generator() {
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#ifdef PRALINE
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// PRALINE: Configure clock input mux GPIO
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// GPIO0_15 (clkin_ctrl) selects GP_CLKIN source:
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// 0 = P1 connector (external)
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// 1 = P22 (internal Si5351 CLK2)
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constexpr GPIO gpio_clkin_ctrl = gpio[GPIO0_15];
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gpio_clkin_ctrl.output();
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gpio_clkin_ctrl.write(1); // CLKIN_SIGNAL_P22 = 1 = internal Si5351 CLK2
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// Also enable MCU clock gate (GPIO0_8)
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gpio_r9_mcu_clk_en.output();
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gpio_r9_mcu_clk_en.write(1);
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#else
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// HackRF One r9: GPIO0_8 (mcu_clk_en) gates Si5351 CLK2/CLK7 to GP_CLKIN
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if (hackrf_r9) {
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gpio_r9_mcu_clk_en.output();
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gpio_r9_mcu_clk_en.write(1);
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}
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#endif
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clock_generator.reset();
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clock_generator.set_crystal_internal_load_capacitance(CrystalInternalLoadCapacitance::XTAL_CL_8pF);
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clock_generator.enable_fanout();
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#ifdef PRALINE
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/* PRALINE has Si5351A (NOT Si5351C like HackRF One OG).
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* Must use Si5351A configuration: PLLA only, no CLKIN support.
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*
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* IMPORTANT: Follow HackRF reference sequence:
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* 1. Set PLL input sources
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* 2. Configure PLL and multisynths
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* 3. Set clock control registers (AFTER multisynths!)
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* 4. Reset PLLs
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* 5. Enable outputs
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*/
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clock_generator.set_pll_input_sources(si5351a_pll_input_sources);
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/* Skip MCU CLKIN setup and reference detection for PRALINE - not applicable */
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reference = Reference{ReferenceSource::Xtal, 0};
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/* Clock control will be set AFTER multisynth configuration - see below */
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#else
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clock_generator.set_pll_input_sources(hackrf_r9
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? si5351a_pll_input_sources
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: si5351c_pll_input_sources);
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@@ -298,7 +374,62 @@ void ClockManager::init_clock_generator() {
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si5351_clock_control_common[7].ms_src(ref_pll),
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}};
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clock_generator.set_clock_control(si5351_clock_control);
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#endif
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#ifdef PRALINE
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/* PRALINE uses Si5351A with:
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* CLK0 = AFE_CLK (codec/FPGA sample clock)
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* CLK1 = SCT_CLK (FPGA timing clock at 2x sample rate)
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* CLK4 = first IF (RFFC5072)
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* CLK5 = second IF (MAX2831)
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* Uses PLLA on XTAL only (no CLKIN support).
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*/
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/* Step 1: Write PLL A configuration (800 MHz VCO from 25 MHz XTAL) */
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/* Use single-byte writes to debug I2C issues */
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{
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const auto& pll_regs = si5351_pll_a_xtal_reg;
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const uint8_t base_reg = pll_regs[0];
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for (size_t i = 1; i < pll_regs.size(); i++) {
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clock_generator.write_register(base_reg + i - 1, pll_regs[i]);
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}
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}
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/* Step 2: Write multisynth configurations using single-byte writes */
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clock_generator.write_ms_single_byte(0, si5351_ms_0_8m); // MS0 = divider 50, r_div=1 for 8 MHz
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clock_generator.write_ms_single_byte(1, si5351_ms_16m); // MS1 = divider 50, r_div=0 for 16 MHz
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/* CLK4 and CLK5 - use single-byte writes too */
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{
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const auto& ms4_regs = si5351c_ms_4_reg;
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const uint8_t base_reg = ms4_regs[0];
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for (size_t i = 1; i < ms4_regs.size(); i++) {
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clock_generator.write_register(base_reg + i - 1, ms4_regs[i]);
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}
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}
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{
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const auto& ms5_regs = si5351c_ms_5_reg;
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const uint8_t base_reg = ms5_regs[0];
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for (size_t i = 1; i < ms5_regs.size(); i++) {
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clock_generator.write_register(base_reg + i - 1, ms5_regs[i]);
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}
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}
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clock_generator.write(si5351a_ms6_7_off_reg); // MS6/7 off - short write is OK
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/* Step 3: NOW set clock control registers (AFTER multisynths per HackRF reference) */
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const auto ref_pll = ClockControl::MultiSynthSource::PLLA;
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const ClockControls si5351_clock_control = ClockControls{{
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si5351a_clock_control_common[0].ms_src(ref_pll),
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si5351a_clock_control_common[1].ms_src(ref_pll),
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si5351a_clock_control_common[2].ms_src(ref_pll),
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si5351a_clock_control_common[3].ms_src(ref_pll),
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si5351a_clock_control_common[4].ms_src(ref_pll),
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si5351a_clock_control_common[5].ms_src(ref_pll),
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si5351a_clock_control_common[6].ms_src(ref_pll),
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si5351a_clock_control_common[7].ms_src(ref_pll),
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}};
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clock_generator.set_clock_control(si5351_clock_control);
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#else
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if (hackrf_r9) {
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const PLLReg pll_reg = (reference.source == ReferenceSource::Xtal)
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? si5351_pll_a_xtal_reg
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@@ -319,21 +450,45 @@ void ClockManager::init_clock_generator() {
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clock_generator.write(si5351c_ms_5_reg);
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clock_generator.write(si5351c_ms6_7_off_mcu_clkin_reg);
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}
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#endif
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clock_generator.reset_plls();
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// Wait for PLL(s) to lock.
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#ifdef PRALINE
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// PRALINE: Wait for PLLA to lock (0x20 = LOL_A bit)
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uint8_t device_status_mask = 0x20;
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uint32_t pll_timeout = 100000;
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while ((clock_generator.device_status() & device_status_mask) != 0 && pll_timeout > 0) {
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pll_timeout--;
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}
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// Store PLL lock status for debugging
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static volatile uint32_t pll_lock_timeout = pll_timeout;
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(void)pll_lock_timeout;
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// CRITICAL: Add delay to ensure Si5351 writes complete before I2C bus stops
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chThdSleepMilliseconds(100);
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#else
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// Wait for PLL(s) to lock - with timeout to prevent hang
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uint8_t device_status_mask = hackrf_r9
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? 0x20
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: (ref_pll == ClockControl::MultiSynthSource::PLLB)
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? 0x40
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: 0x20;
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#ifndef PRALINE
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while ((clock_generator.device_status() & device_status_mask) != 0);
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#else
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uint32_t pll_timeout = 100000;
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while ((clock_generator.device_status() & device_status_mask) != 0 && pll_timeout > 0) {
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pll_timeout--;
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}
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#endif
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clock_generator.set_clock_control(
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clock_generator_output_mcu_clkin,
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si5351_clock_control_common[clock_generator_output_mcu_clkin].ms_src(ref_pll).clk_pdn(ClockControl::ClockPowerDown::Power_On));
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clock_generator.enable_output(clock_generator_output_mcu_clkin);
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#endif
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}
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uint32_t ClockManager::measure_gp_clkin_frequency() {
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@@ -400,6 +555,15 @@ void ClockManager::shutdown() {
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}
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void ClockManager::enable_codec_clocks() {
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#ifdef PRALINE
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/* PRALINE: CLK0 (AFE_CLK) for codec/FPGA, CLK1 (SCT_CLK) for FPGA timing.
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* Reference hackrf_core.c shows PRALINE needs both CLK0 and CLK1. */
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clock_generator.enable_clock(clock_generator_output_og_codec); /* CLK0 */
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clock_generator.enable_clock(clock_generator_output_og_cpld); /* CLK1 */
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clock_generator.enable_output_mask(
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(1U << clock_generator_output_og_codec) |
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(1U << clock_generator_output_og_cpld));
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#else
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if (hackrf_r9) {
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clock_generator.enable_clock(clock_generator_output_r9_sgpio);
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} else {
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@@ -417,6 +581,7 @@ void ClockManager::enable_codec_clocks() {
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clock_generator.enable_output_mask(
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(1U << clock_generator_output_og_codec) | (1U << clock_generator_output_og_cpld) | (1U << clock_generator_output_og_sgpio));
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}
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#endif
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}
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void ClockManager::disable_codec_clocks() {
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@@ -424,6 +589,14 @@ void ClockManager::disable_codec_clocks() {
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* be enabled for the output to come to rest at the state specified by
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* CLKx_DISABLE_STATE.
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*/
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#ifdef PRALINE
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/* PRALINE: CLK0 (AFE_CLK) and CLK1 (SCT_CLK) used for codec/FPGA */
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clock_generator.disable_output_mask(
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(1U << clock_generator_output_og_codec) |
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(1U << clock_generator_output_og_cpld));
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clock_generator.disable_clock(clock_generator_output_og_codec);
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clock_generator.disable_clock(clock_generator_output_og_cpld);
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#else
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if (hackrf_r9) {
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clock_generator.disable_output_mask(1U << clock_generator_output_r9_sgpio);
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clock_generator.disable_clock(clock_generator_output_r9_sgpio);
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@@ -434,9 +607,17 @@ void ClockManager::disable_codec_clocks() {
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clock_generator.disable_clock(clock_generator_output_og_cpld);
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clock_generator.disable_clock(clock_generator_output_og_sgpio);
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}
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#endif
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}
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void ClockManager::enable_if_clocks() {
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#ifdef PRALINE
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/* PRALINE uses CLK4 (first IF) and CLK5 (second IF) like original HackRF One */
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clock_generator.enable_clock(clock_generator_output_og_first_if);
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clock_generator.enable_output_mask(1U << clock_generator_output_og_first_if);
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clock_generator.enable_clock(clock_generator_output_og_second_if);
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clock_generator.enable_output_mask(1U << clock_generator_output_og_second_if);
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#else
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if (hackrf_r9) {
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clock_generator.enable_clock(clock_generator_output_r9_if);
|
||||
clock_generator.enable_output_mask(1U << clock_generator_output_r9_if);
|
||||
@@ -446,9 +627,16 @@ void ClockManager::enable_if_clocks() {
|
||||
clock_generator.enable_clock(clock_generator_output_og_second_if);
|
||||
clock_generator.enable_output_mask(1U << clock_generator_output_og_second_if);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void ClockManager::disable_if_clocks() {
|
||||
#ifdef PRALINE
|
||||
clock_generator.disable_output_mask(1U << clock_generator_output_og_first_if);
|
||||
clock_generator.disable_clock(clock_generator_output_og_first_if);
|
||||
clock_generator.disable_output_mask(1U << clock_generator_output_og_second_if);
|
||||
clock_generator.disable_clock(clock_generator_output_og_second_if);
|
||||
#else
|
||||
if (hackrf_r9) {
|
||||
clock_generator.disable_output_mask(1U << clock_generator_output_r9_if);
|
||||
clock_generator.disable_clock(clock_generator_output_r9_if);
|
||||
@@ -458,19 +646,39 @@ void ClockManager::disable_if_clocks() {
|
||||
clock_generator.disable_output_mask(1U << clock_generator_output_og_second_if);
|
||||
clock_generator.disable_clock(clock_generator_output_og_second_if);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void ClockManager::set_sampling_frequency(const uint32_t frequency) {
|
||||
#ifdef PRALINE
|
||||
/* PRALINE: CLK0=AFE_CLK runs at sample rate (VCO/divider/2)
|
||||
* CLK1=SCT_CLK runs at 2x sample rate (VCO/divider/1)
|
||||
* Reference: hackrf_core.c sample_rate_frac_set() lines 580-582
|
||||
*/
|
||||
|
||||
/* PRALINE: Match HackRF USB sample_rate_frac_set()
|
||||
* Reference: hackrf_usb radio.c lines 29-91, hackrf_core.c lines 501-685 */
|
||||
|
||||
// Set FPGA decimation to 0 (no decimation) for direct passthrough
|
||||
fpga_debug_register_write(2, 0);
|
||||
radio::invalidate_spi_config();
|
||||
|
||||
// The following was originally from @kitty. Adopting for testing radio.
|
||||
clock_generator.set_ms_frequency(0, frequency * 2, si5351_vco_f, 1); // CLK0: r_div=1 (÷2)
|
||||
clock_generator.set_ms_frequency(1, frequency * 2, si5351_vco_f, 0); // CLK1: r_div=0 (÷1)
|
||||
#else
|
||||
/* Codec clock is at sampling frequency, CPLD and SGPIO clocks are at
|
||||
* twice the frequency, and derived from the MS0 synth. So it's only
|
||||
* necessary to change the MS0 synth frequency, and ensure the output
|
||||
* is divided by two.
|
||||
*/
|
||||
|
||||
if (hackrf_r9) {
|
||||
clock_generator.set_ms_frequency(clock_generator_output_r9_sgpio, frequency * 2, si5351_vco_f, 0);
|
||||
} else {
|
||||
clock_generator.set_ms_frequency(clock_generator_output_og_codec, frequency * 2, si5351_vco_f, 1);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void ClockManager::set_reference_ppb(const int32_t ppb) {
|
||||
@@ -510,7 +718,15 @@ void ClockManager::start_frequency_monitor_measurement(const cgu::CLK_SEL clk_se
|
||||
|
||||
void ClockManager::wait_For_frequency_monitor_measurement_done() {
|
||||
// FREQ_MON mechanism fails to finish if there's no clock present on selected input?!
|
||||
#ifndef PRALINE
|
||||
while (LPC_CGU->FREQ_MON.MEAS == 1);
|
||||
#else
|
||||
// PRALINE FIX: Add timeout to prevent infinite hang
|
||||
uint32_t timeout = 100000;
|
||||
while (LPC_CGU->FREQ_MON.MEAS == 1 && timeout > 0) {
|
||||
timeout--;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
uint32_t ClockManager::get_frequency_monitor_measurement_in_hertz() {
|
||||
@@ -521,6 +737,35 @@ uint32_t ClockManager::get_frequency_monitor_measurement_in_hertz() {
|
||||
}
|
||||
|
||||
void ClockManager::start_audio_pll() {
|
||||
#ifdef PRALINE
|
||||
/* PRALINE: Use 12MHz XTAL for audio PLL
|
||||
* For 12MHz XTAL input, 48kHz audio rate, 256Fs MCLK:
|
||||
* Fout=12.288MHz, Fcco=491.52MHz
|
||||
* 12MHz * 1024 / 25 = 491.52MHz
|
||||
* MSEL=1024, NSEL=25, PSEL=20
|
||||
*/
|
||||
cgu::pll0audio::ctrl({
|
||||
.pd = 1,
|
||||
.bypass = 0,
|
||||
.directi = 0,
|
||||
.directo = 0,
|
||||
.clken = 0,
|
||||
.frm = 0,
|
||||
.autoblock = 1,
|
||||
.pllfract_req = 0,
|
||||
.sel_ext = 1,
|
||||
.mod_pd = 1,
|
||||
.clk_sel = cgu::CLK_SEL::XTAL,
|
||||
});
|
||||
|
||||
cgu::pll0audio::mdiv({
|
||||
.mdec = 22625UL, // MDEC for MSEL=1024
|
||||
});
|
||||
cgu::pll0audio::np_div({
|
||||
.pdec = 31, // PSEL=20
|
||||
.ndec = 69, // NDEC for NSEL=25
|
||||
});
|
||||
#else
|
||||
cgu::pll0audio::ctrl({
|
||||
.pd = 1,
|
||||
.bypass = 0,
|
||||
@@ -549,13 +794,24 @@ void ClockManager::start_audio_pll() {
|
||||
.pdec = 31,
|
||||
.ndec = 45,
|
||||
});
|
||||
#endif
|
||||
|
||||
cgu::pll0audio::frac({
|
||||
.pllfract_ctrl = 0,
|
||||
});
|
||||
|
||||
cgu::pll0audio::power_up();
|
||||
#ifndef PRALINE
|
||||
while (!cgu::pll0audio::is_locked());
|
||||
#else
|
||||
// PRALINE FIX: Add timeout to prevent infinite hang if GP_CLKIN not present
|
||||
{
|
||||
uint32_t timeout = 100000;
|
||||
while (!cgu::pll0audio::is_locked() && timeout > 0) {
|
||||
timeout--;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
cgu::pll0audio::clock_enable();
|
||||
|
||||
set_base_audio_clock_divider(1);
|
||||
|
||||
Reference in New Issue
Block a user