mirror of
https://github.com/portapack-mayhem/mayhem-firmware.git
synced 2026-09-10 16:49:36 +00:00
Gpio modify v3 (#3238)
* Refactor GPIO mappings and definitions for improved clarity and functionality - Updated SCU_ARRAY_SIZE definitions in pal_lld.h for PRALINE and non-PRALINE configurations. - Modified pin mappings in gpio.hpp to reflect new hardware configurations, including additional control pins for RF and audio components. - Removed obsolete GPIO definitions from hackrf_gpio.hpp and streamlined the code for better maintainability. - Added new GPIO definitions for mix bypass, amplifier control, and other RF-related functionalities to enhance the system's capabilities. * Refactor GPIO mappings and update SCU_ARRAY_SIZE for LPC43xx platform - Updated SCU_ARRAY_SIZE to 80 for PRALINE configuration and 58 for others. - Added new GPIO mappings for auxiliary power control, antenna bias, and R9 clock enable signals in gpio.hpp. - Removed commented-out PPS output mapping in hackrf_gpio.hpp. - Adjusted GPIO definitions for R9 clock signals to ensure proper functionality. * Refactor RF path initialization and configuration for improved clarity and functionality * Refactor RF path configuration and GPIO mappings for improved clarity and functionality * Potential fix for pull request finding * comment * aux power polarrity * Fix formatting of pin_aux_power_enable declaration
This commit is contained in:
Pezsma
GitHub
@@ -57,55 +57,49 @@ const PALConfig pal_default_config = {
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// GPIO0
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.data
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#ifdef PRALINE
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= (0 << 7) // P2_7: Input GND
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| (0 << 8) // P1_1: Input GND
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| (1 << 9) // P1_2: Input VCC
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| boot_bit(p1_ctrl0, 0) // P2_10: P1_CTRL0, start low
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= boot_bit(p1_ctrl0, 0) // P2_10: P1_CTRL0, start low
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| boot_bit(clkin_ctrl, 0) // P1_20: CLKIN_CTRL - start low
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#else
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= (1 << 14) // P2_10: AMP_BYPASS
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| (1 << 15) // P1_20: CS_XCVR
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= boot_bit(amp_bypass, 1) // P2_10: AMP_BYPASS
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| (1 << 15) // P1_20: CS_XCVR
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#endif
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| (1 << 11) // P1_4: SSP1_MOSI
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| boot_bit(sgpio_12, 0) // P1_18: SGPIO12, HOST_Q_INVERT
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| boot_bit(sgpio_11, 0) // P1_17: SGPIO11, HOST_DIRECTION, Praline: FPGA HOST_DIRECTION
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| (1 << 10) // P1_3: SSP1_MISO
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| (0 << 9) // P1_2: Varies by revision, float until detection
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| (0 << 8) // P1_1: Varies by revision, float until detection
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| (0 << 7) // P2_7: Varies by revision, float until detection
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| (0 << 6) // P3_6: SPIFI_MISO
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| boot_bit(sgpio_5, 1) // P6_6: SGPIO5, HOST_DATA5, Praline: FPGA HOST_DATA5
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| boot_bit(sgpio_7, 1) // P1_0: SGPIO7, HOST_DATA7, Praline: FPGA HOST_DATA7
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| boot_bit(sgpio_3, 1) // P1_16: SGPIO3, HOST_DATA3, Praline: FPGA HOST_DATA3
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| boot_bit(sgpio_2, 1) // P1_15: SGPIO2, HOST_DATA2, Praline: FPGA HOST_DATA2
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| boot_bit(sgpio_1, 1) // P0_1: SGPIO1, HOST_DATA1, Praline: FPGA HOST_DATA1
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| boot_bit(sgpio_0, 1) // P0_0: SGPIO0, HOST_DATA0, Praline: FPGA HOST_DATA0
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| boot_bit(dfu_boot_0, 0) // P1_1: 10K PU, BOOT0
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| boot_bit(dfu_boot_1, 0) // P1_2: 10K PD, BOOT1
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| boot_bit(dfu_isp, 0) // P2_7: 10K PU, ISP
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| (1 << 11) // P1_4: SSP1_MOSI
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| boot_bit(sgpio_12, 0) // P1_18: SGPIO12, HOST_Q_INVERT
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| boot_bit(sgpio_11, 0) // P1_17: SGPIO11, HOST_DIRECTION, Praline: FPGA HOST_DIRECTION
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| (1 << 10) // P1_3: SSP1_MISO
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| (0 << 6) // P3_6: SPIFI_MISO
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| boot_bit(sgpio_5, 1) // P6_6: SGPIO5, HOST_DATA5, Praline: FPGA HOST_DATA5
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| boot_bit(sgpio_7, 1) // P1_0: SGPIO7, HOST_DATA7, Praline: FPGA HOST_DATA7
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| boot_bit(sgpio_3, 1) // P1_16: SGPIO3, HOST_DATA3, Praline: FPGA HOST_DATA3
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| boot_bit(sgpio_2, 1) // P1_15: SGPIO2, HOST_DATA2, Praline: FPGA HOST_DATA2
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| boot_bit(sgpio_1, 1) // P0_1: SGPIO1, HOST_DATA1, Praline: FPGA HOST_DATA1
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| boot_bit(sgpio_0, 1) // P0_0: SGPIO0, HOST_DATA0, Praline: FPGA HOST_DATA0
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,
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.dir
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#ifdef PRALINE
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= (0 << 7) // P2_7: Input
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| (0 << 8) // P1_1: Input
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| (0 << 9) // P1_2: Input
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| boot_bit(p1_ctrl0, 1) // P2_10: P1_CTRL0
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= boot_bit(p1_ctrl0, 1) // P2_10: P1_CTRL0
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| boot_bit(clkin_ctrl, 1) // P1_20: CLKIN_CTRL
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#else
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= (1 << 14) // P2_10: AMP_BYPASS
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| (1 << 15) // P1_20: CS_XCVR
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= boot_bit(amp_bypass, 1) // P2_10: AMP_BYPASS
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| (1 << 15) // P1_20: CS_XCVR
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#endif
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| (0 << 11) // P1_4: SSP1_MOSI
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| boot_bit(sgpio_12, 1) // P1_18: SGPIO12, HOST_Q_INVERT
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| boot_bit(sgpio_11, 0) // P1_17: SGPIO11, HOST_DIRECTION, Praline: FPGA HOST_DIRECTION
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| (0 << 10) // P1_3: SSP1_MISO
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| (0 << 9) // P1_2: Varies by revision, float until detection
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| (0 << 8) // P1_1: Varies by revision, float until detection
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| (0 << 7) // P2_7: Varies by revision, float until detection
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| (0 << 6) // P3_6: SPIFI_MISO
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| boot_bit(sgpio_5, 1) // P6_6: SGPIO5, HOST_DATA5
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| boot_bit(sgpio_7, 1) // P1_0: SGPIO7, HOST_DATA7
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| boot_bit(sgpio_3, 0) // P1_16: SGPIO3, HOST_DATA3
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| boot_bit(sgpio_2, 0) // P1_15: SGPIO2, HOST_DATA2
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| boot_bit(sgpio_1, 0) // P0_1: SGPIO1, HOST_DATA1
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| boot_bit(sgpio_0, 0) // P0_0: SGPIO0, HOST_DATA0
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| boot_bit(dfu_boot_0, 0) // P1_1: 10K PU, BOOT0
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| boot_bit(dfu_boot_1, 0) // P1_2: 10K PD, BOOT1
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| boot_bit(dfu_isp, 0) // P2_7: 10K PU, ISP
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| (0 << 10) // P1_3: SSP1_MISO
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| (0 << 11) // P1_4: SSP1_MOSI
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| boot_bit(sgpio_12, 1) // P1_18: SGPIO12, HOST_Q_INVERT
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| boot_bit(sgpio_11, 0) // P1_17: SGPIO11, HOST_DIRECTION, Praline: FPGA HOST_DIRECTION
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| (0 << 6) // P3_6: SPIFI_MISO
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| boot_bit(sgpio_5, 1) // P6_6: SGPIO5, HOST_DATA5
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| boot_bit(sgpio_7, 1) // P1_0: SGPIO7, HOST_DATA7
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| boot_bit(sgpio_3, 0) // P1_16: SGPIO3, HOST_DATA3
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| boot_bit(sgpio_2, 0) // P1_15: SGPIO2, HOST_DATA2
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| boot_bit(sgpio_1, 0) // P0_1: SGPIO1, HOST_DATA1
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| boot_bit(sgpio_0, 0) // P0_0: SGPIO0, HOST_DATA0
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},
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{
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// GPIO1
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@@ -113,55 +107,55 @@ const PALConfig pal_default_config = {
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| (1 << 14) // P3_4: SPIFI_SIO3
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| (1 << 13) // P2_13: PortaPack DIR
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#ifdef PRALINE
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| (1 << 12) // P2_12: BIAS_EN
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| (0 << 11) // P2_11: BIAS_OC
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| boot_bit(aa_en, 0) // P1_14: AA_EN
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| (0 << 0) // P1_7: Output GND
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| boot_bit(ant_bias, 1) // P2_12: !BIAS_EN
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| boot_bit(ant_bias_oc, 0) // P2_11: BIAS_OC
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| boot_bit(aa_en, 0) // P1_14: AA_EN
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| (0 << 0) // P1_7: Output GND
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#else
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| (1 << 12) // P2_12: !RX_AMP_PWR
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| (0 << 11) // P2_11: RX_AMP
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| boot_bit(sgpio_10, 1) // P1_14: SGPIO10, HOST_DISABLE
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| (0 << 0) // P1_7: !MIX_BYPASS
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| boot_bit(rx_amp_pwr, 1) // P2_12: !RX_AMP_PWR
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| boot_bit(rx_amp, 0) // P2_11: RX_AMP
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| boot_bit(sgpio_10, 1) // P1_14: SGPIO10, HOST_DISABLE
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| boot_bit(tx_mix_bypass, 1) // P1_7: !TX MIX BYPASS
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#endif
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| (0 << 10) // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
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| (1 << 9) // P1_6: SD_CMD
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| (1 << 8) // P1_5: SD_POW, PortaPack CPLD.TDO(O)
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| (1 << 6) // P1_13: SD_CD
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| (1 << 5) // P1_12: SD_DAT3
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| (1 << 4) // P1_11: SD_DAT2
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| (1 << 3) // P1_10: SD_DAT1
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| (1 << 2) // P1_9: SD_DAT0
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| (1 << 1) // P1_8: PortaPack CPLD.TMS(I)
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| boot_bit(lcd_wrx, 0) // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
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| (1 << 9) // P1_6: SD_CMD
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| (1 << 8) // P1_5: SD_POW, PortaPack CPLD.TDO(O)
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| (1 << 6) // P1_13: SD_CD
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| (1 << 5) // P1_12: SD_DAT3
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| (1 << 4) // P1_11: SD_DAT2
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| (1 << 3) // P1_10: SD_DAT1
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| (1 << 2) // P1_9: SD_DAT0
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| (1 << 1) // P1_8: PortaPack CPLD.TMS(I)
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,
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.dir = (0 << 15) // P3_5: SPIFI_SIO2
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| (0 << 14) // P3_4: SPIFI_SIO3
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| (1 << 13) // P2_13: PortaPack DIR
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#ifdef PRALINE
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| (1 << 12) // P2_12: !BIAS_EN
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| (0 << 11) // P2_11: BIAS_OC
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| boot_bit(aa_en, 1) // P1_14: AA_EN
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| (1 << 0) // P1_7: Output
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| boot_bit(ant_bias, 1) // P2_12: !BIAS_EN
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| boot_bit(ant_bias_oc, 0) // P2_11: BIAS_OC
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| boot_bit(aa_en, 1) // P1_14: AA_EN
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| (1 << 0) // P1_7: Output
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#else
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| (1 << 12) // P2_12: !RX_AMP_PWR
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| (1 << 11) // P2_11: RX_AMP
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| boot_bit(sgpio_10, 0) // P1_14: SGPIO10, HOST_DISABLE
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| (1 << 0) // P1_7: !MIX_BYPASS
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| boot_bit(rx_amp_pwr, 1) // P2_12: !RX_AMP_PWR
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| boot_bit(rx_amp, 1) // P2_11: RX_AMP
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| boot_bit(sgpio_10, 0) // P1_14: SGPIO10, HOST_DISABLE
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| boot_bit(tx_mix_bypass, 1) // P1_7: !TX MIX BYPASS
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#endif
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| (1 << 10) // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
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| (0 << 9) // P1_6: SD_CMD
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| (0 << 8) // P1_5: SD_POW, PortaPack CPLD.TDO(O)
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| (0 << 6) // P1_13: SD_CD
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| (0 << 5) // P1_12: SD_DAT3
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| (0 << 4) // P1_11: SD_DAT2
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| (0 << 3) // P1_10: SD_DAT1
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| (0 << 2) // P1_9: SD_DAT0
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| (0 << 1) // P1_8: PortaPack CPLD.TMS(I)
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| boot_bit(lcd_wrx, 1) // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
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| (0 << 9) // P1_6: SD_CMD
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| (0 << 8) // P1_5: SD_POW, PortaPack CPLD.TDO(O)
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| (0 << 6) // P1_13: SD_CD
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| (0 << 5) // P1_12: SD_DAT3
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| (0 << 4) // P1_11: SD_DAT2
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| (0 << 3) // P1_10: SD_DAT1
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| (0 << 2) // P1_9: SD_DAT0
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| (0 << 1) // P1_8: PortaPack CPLD.TMS(I)
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},
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{
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// GPIO2
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.data = (0 << 15) // P5_6: TX_AMP, unused on PRALINE
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| (1 << 14) // P5_5: MIXER_RESETX, 10K PU
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.data = (1 << 14) // P5_5: MIXER_RESETX, 10K PU
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#ifdef PRALINE
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| (0 << 15) // P5_6: unused on PRALINE
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| (1 << 13) // P5_4: RFFC5072 ENX
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| (0 << 12) // P5_3: unused on PRALINE
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| (0 << 11) // P5_2: FPGA_CRESET
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@@ -175,51 +169,53 @@ const PALConfig pal_default_config = {
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| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
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| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
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#else
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| (1 << 13) // P5_4: MIXER_ENX, 10K PU
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| (1 << 12) // P5_3: RX_MIX_BP
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| (0 << 11) // P5_2: TX_MIX_BP
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| (0 << 10) // P5_1: LP
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| (0 << 4) // P4_4: Varies by revision
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| (0 << 9) // P5_0: Varies by revision
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| (1 << 0) // P4_0: HP
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| boot_bit(sgpio_9, 1) // P4_3: SGPIO9, HOST_CAPTURE
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| (0 << 6) // P4_6: XCVR_EN, 10K PD
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| boot_bit(led_tx, 0) // P6_12: LED3 (TX)
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| boot_bit(led_rx, 0) // P4_2: LED2 (RX)
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| boot_bit(led_usb, 0) // P4_1: LED1 (USB)
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| boot_bit(tx_amp, 0) // P5_6: TX_AMP
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| (1 << 13) // P5_4: MIXER_ENX, 10K PU
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| boot_bit(rx_mix_bp, 1) // P5_3: RX_MIX_BP
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| boot_bit(tx_mix_bp, 0) // P5_2: TX_MIX_BP
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| boot_bit(lpf, 0) // P5_1: LPF
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| (0 << 9) // P5_0: Varies by revision
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| boot_bit(hpf, 0) // P4_0: HPF
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| boot_bit(sgpio_9, 1) // P4_3: SGPIO9, HOST_CAPTURE
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| (0 << 6) // P4_6: XCVR_EN, 10K PD
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| boot_bit(led_tx, 0) // P6_12: LED3 (TX)
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| boot_bit(led_rx, 0) // P4_2: LED2 (RX)
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| boot_bit(led_usb, 0) // P4_1: LED1 (USB)
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#endif
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| (1 << 7) // P5_7: CS_AD
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| (0 << 5) // P4_5: RXENABLE
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,
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.dir = (1 << 15) // P5_6: TX_AMP, unused on PRALINE
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.dir =
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#ifdef PRALINE
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| (1 << 13) // P5_4: RFFC5072 ENX
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| (1 << 12) // P5_3: unused on PRALINE
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| (1 << 11) // P5_2: FPGA_CRESET
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| (1 << 10) // P5_1: FPGA_SPI_CS
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| (1 << 4) // P4_4: unused on PRALINE
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| (1 << 9) // P5_0: unused on PRALINE
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| (1 << 0) // P4_0: unused on PRALINE
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| (0 << 3) // P4_3: VBUSCTRL input
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| (0 << 6) // P4_6: Input
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(1 << 15) // P5_6: unused on PRALINE
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| (1 << 13) // P5_4: RFFC5072 ENX
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| (1 << 12) // P5_3: unused on PRALINE
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| (1 << 11) // P5_2: FPGA_CRESET
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| (1 << 10) // P5_1: FPGA_SPI_CS
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| (1 << 4) // P4_4: unused on PRALINE
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| (1 << 9) // P5_0: unused on PRALINE
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| (1 << 0) // P4_0: unused on PRALINE
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| (0 << 3) // P4_3: VBUSCTRL input
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| (0 << 6) // P4_6: Input
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#else
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| (1 << 13) // P5_4: MIXER_ENX, 10K PU
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| (1 << 12) // P5_3: RX_MIX_BP
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| (1 << 11) // P5_2: TX_MIX_BP
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| (1 << 10) // P5_1: LP
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| (0 << 4) // P4_4: Varies by revision
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| (0 << 9) // P5_0: Varies by revision
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| (1 << 0) // P4_0: HP
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| boot_bit(sgpio_9, 0) // P4_3: SGPIO9, HOST_CAPTURE
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| (1 << 6) // P4_6: XCVR_EN, 10K PD
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boot_bit(tx_amp, 1) // P5_6: TX_AMP
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| (1 << 13) // P5_4: MIXER_ENX, 10K PU
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| boot_bit(rx_mix_bp, 1) // P5_3: RX_MIX_BP
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| boot_bit(tx_mix_bp, 1) // P5_2: TX_MIX_BP
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| boot_bit(lpf, 1) // P5_1: LPF
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| (0 << 9) // P5_0: Varies by revision
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| boot_bit(hpf, 1) // P4_0: HPF
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| boot_bit(sgpio_9, 0) // P4_3: SGPIO9, HOST_CAPTURE
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| (1 << 6) // P4_6: XCVR_EN, 10K PD
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#endif
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| (1 << 14) // P5_5: MIXER_RESETX, 10K PU
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| boot_bit(led_tx, 1) // P6_12: LED3 (TX)
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| (1 << 7) // P5_7: CS_AD
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| (1 << 5) // P4_5: RXENABLE
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| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
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| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
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| (1 << 14) // P5_5: MIXER_RESETX, 10K PU
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| boot_bit(led_tx, 1) // P6_12: LED3 (TX)
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| (1 << 7) // P5_7: CS_AD
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| (1 << 5) // P4_5: RXENABLE
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| boot_bit(led_rx, 1) // P4_2: LED2 (RX)
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| boot_bit(led_usb, 1) // P4_1: LED1 (USB)
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},
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{
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// GPIO3
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@@ -232,16 +228,17 @@ const PALConfig pal_default_config = {
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| (1 << 9) // P7_1: PortaPack GPIO3_9(IO)
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| (1 << 8) // P7_0: PortaPack GPIO3_8(IO)
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#ifdef PRALINE
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| (0 << 4) // P6_5: TX_ENABLE
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| (1 << 2) // P6_3: MIX_ENABLE_N
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| (0 << 6) // P6_10: unused on PRALINE
|
||||
| boot_bit(p1_ctrl2, 0) // P6_9: P1_CTRL2
|
||||
| boot_bit(tx_enable, 0) // P6_5: TX_ENABLE
|
||||
| boot_bit(mix_bypass, 1) // P6_3: MIX_ENABLE_N
|
||||
| (0 << 6) // P6_10: unused on PRALINE
|
||||
| boot_bit(p1_ctrl2, 0) // P6_9: P1_CTRL2
|
||||
| boot_bit(aux_power_oc, 0) // P6_11: AUX overcurrent
|
||||
#else
|
||||
| (1 << 4) // P6_5: HackRF CPLD.TMS(I)
|
||||
| boot_bit(vregmode, 1) // P6_11: VREGMODE
|
||||
| (0 << 6) // P6_10: Varies by revision
|
||||
| (1 << 2) // P6_3: SGPIO4
|
||||
| (1 << 5) // P6_9: !TX_AMP_PWR, 10K PU
|
||||
| (1 << 4) // P6_5: HackRF CPLD.TMS(I)
|
||||
| boot_bit(vregmode, 1) // P6_11: VREGMODE
|
||||
| (0 << 6) // P6_10: Varies by revision
|
||||
| boot_bit(sgpio_4, 1) // P6_3: SGPIO4
|
||||
| boot_bit(tx_amp_pwr, 1) // P6_9: !TX_AMP_PWR, 10K PU
|
||||
#endif
|
||||
| (1 << 3) // P6_4: MIXER_SDATA
|
||||
| (1 << 1) // P6_2: HackRF CPLD.TDI(I)
|
||||
@@ -256,16 +253,16 @@ const PALConfig pal_default_config = {
|
||||
| (1 << 9) // P7_1: PortaPack GPIO3_9(IO)
|
||||
| (1 << 8) // P7_0: PortaPack GPIO3_8(IO)
|
||||
#ifdef PRALINE
|
||||
| (0 << 7) // P6_11: 3V3AUX_OC
|
||||
| (1 << 4) // P6_5: TX_ENABLE
|
||||
| (1 << 2) // P6_3: MIX_ENABLE_N
|
||||
| (0 << 6) // P6_10: unused on PRALINE
|
||||
| boot_bit(p1_ctrl2, 1) // P6_9: P1_CTRL2
|
||||
| boot_bit(aux_power_oc, 0) // P6_11: AUX overcurrent
|
||||
| boot_bit(tx_enable, 1) // P6_5: TX_ENABLE
|
||||
| boot_bit(mix_bypass, 1) // P6_3: MIX_ENABLE_N
|
||||
| (0 << 6) // P6_10: unused on PRALINE
|
||||
| boot_bit(p1_ctrl2, 1) // P6_9: P1_CTRL2
|
||||
#else
|
||||
| boot_bit(vregmode, 1) // P6_11: VREGMODE
|
||||
| (0 << 6) // P6_10: Varies by revision
|
||||
| (0 << 2) // P6_3: SGPIO4
|
||||
| (1 << 5) // P6_9: !TX_AMP_PWR, 10K PU
|
||||
| boot_bit(vregmode, 1) // P6_11: VREGMODE
|
||||
| (0 << 6) // P6_10: Varies by revision
|
||||
| boot_bit(sgpio_4, 0) // P6_3: SGPIO4
|
||||
| boot_bit(tx_amp_pwr, 1) // P6_9: !TX_AMP_PWR, 10K PU
|
||||
#endif
|
||||
| (0 << 4) // P6_5: HackRF CPLD.TMS(I)
|
||||
| (0 << 3) // P6_4: MIXER_SDATA
|
||||
@@ -277,8 +274,8 @@ const PALConfig pal_default_config = {
|
||||
.data =
|
||||
boot_bit(sgpio_8, 0) // P9_6: SGPIO8, SGPIO_CLK, PRALINE: P8_0
|
||||
#ifdef PRALINE
|
||||
| (0 << 9) // PA_2: RF_AMP_EN
|
||||
| (0 << 8) // PA_1: LPF_EN
|
||||
| boot_bit(rf_amp_enable, 0) // PA_2: RF_AMP_EN
|
||||
| boot_bit(lpf, 0) // PA_1: LPF_EN
|
||||
| boot_bit(en_1v2, 0) // P8_7: EN_1V2
|
||||
| boot_bit(led_mcu, 1) // P8_6: LED4
|
||||
| boot_bit(sgpio_10, 1) // P8_2: SGPIO10, HOST_DISABLE
|
||||
@@ -297,8 +294,8 @@ const PALConfig pal_default_config = {
|
||||
.dir =
|
||||
boot_bit(sgpio_8, 0) // P9_6: SGPIO8, SGPIO_CLK, PRALINE: P8_0
|
||||
#ifdef PRALINE
|
||||
| (1 << 9) // PA_2: RF_AMP_EN
|
||||
| (1 << 8) // PA_1: LPF_EN
|
||||
| boot_bit(rf_amp_enable, 1) // PA_2: RF_AMP_EN
|
||||
| boot_bit(lpf, 1) // PA_1: LPF_EN
|
||||
| boot_bit(en_1v2, 1) // P8_7: EN_1V2
|
||||
| boot_bit(led_mcu, 1) // P8_6: LED4
|
||||
| boot_bit(sgpio_10, 0) // P8_2: SGPIO10, HOST_DISABLE
|
||||
@@ -318,81 +315,77 @@ const PALConfig pal_default_config = {
|
||||
// GPIO5
|
||||
.data =
|
||||
#ifdef PRALINE
|
||||
(0 << 18) // P9_5: RFF5072 SCLK
|
||||
| boot_bit(trigger_out, 0) // P2_6: Trigger out
|
||||
| (0 << 14) // P4_10: FPGA CDONE
|
||||
| (1 << 15) // P6_7: 3V3 AUX_ENABLE
|
||||
| boot_bit(p1_ctrl1, 0) // P6_8: P1_CTRL1
|
||||
| boot_bit(sgpio_4, 1) // P9_4: FPGA SGPIO4
|
||||
| (0 << 19) // PA_4: Output GND
|
||||
| (0 << 20) // PB_0: Output GND
|
||||
| (0 << 21) // PB_1: Output GND
|
||||
| (0 << 22) // PB_2: Unused IN
|
||||
| (0 << 23) // PB_3: Output GND
|
||||
| (0 << 24) // PB_4: Unused IN
|
||||
| (0 << 25) // PB_5: Output GND
|
||||
| (0 << 5) // P2_5: PPS OUT/IN
|
||||
| (0 << 12) // P4_8: Output GND
|
||||
| boot_bit(vregmode, 1) // P4_9: TPS62410 VREGMODE
|
||||
(0 << 18) // P9_5: RFF5072 SCLK
|
||||
| boot_bit(trigger_out, 0) // P2_6: Trigger out
|
||||
| (0 << 14) // P4_10: FPGA CDONE
|
||||
| boot_bit(aux_power_enable, 1) // P6_7: !3V3 AUX_ENABLE
|
||||
| boot_bit(p1_ctrl1, 0) // P6_8: P1_CTRL1
|
||||
| boot_bit(sgpio_4, 1) // P9_4: FPGA SGPIO4
|
||||
| (0 << 19) // PA_4: Output GND
|
||||
| (0 << 20) // PB_0: Output GND
|
||||
| (0 << 21) // PB_1: Output GND
|
||||
| (0 << 22) // PB_2: Unused IN
|
||||
| (0 << 23) // PB_3: Output GND
|
||||
| (0 << 24) // PB_4: Unused IN
|
||||
| (0 << 25) // PB_5: Output GND
|
||||
| boot_bit(pps_in_out, 0) // P2_5: PPS OUT/IN
|
||||
| (0 << 12) // P4_8: Output GND
|
||||
| boot_bit(vregmode, 1) // P4_9: TPS62410 VREGMODE
|
||||
#else
|
||||
(1 << 18) // P9_5: HackRF CPLD.TDO(O)
|
||||
| (0 << 6) // P2_6: MIXER_SCLK
|
||||
| (1 << 14) // P4_10: SGPIO15, CPLD (unused)
|
||||
| (0 << 15) // P6_7: Varies by revision
|
||||
| (0 << 5) // P2_5: Varies by revision
|
||||
| (1 << 16) // P6_8: MIX_BYPASS
|
||||
| (1 << 13) // P4_9: SGPIO14, CPLD (unused)
|
||||
| (0 << 12) // P4_8: Varies by revision
|
||||
(1 << 18) // P9_5: HackRF CPLD.TDO(O)
|
||||
| (0 << 6) // P2_6: MIXER_SCLK
|
||||
| (1 << 14) // P4_10: SGPIO15, CPLD (unused)
|
||||
| boot_bit(rx_mix_bypass, 1) // P6_8: RX MIX BYPASS
|
||||
| (1 << 13) // P4_9: SGPIO14, CPLD (unused)
|
||||
| (0 << 12) // P4_8: Varies by revision
|
||||
#endif
|
||||
| (1 << 11) // P3_8: SPIFI_CS
|
||||
| (1 << 10) // P3_7: SPIFI_MOSI
|
||||
| (1 << 9) // P3_2: I2S0_RX_SDA
|
||||
| (1 << 8) // P3_1: I2S0_RX_WS
|
||||
| (0 << 7) // P2_8: BOOT2
|
||||
| (1 << 4) // P2_4: PortaPack LCD_RDX
|
||||
| (0 << 3) // P2_3: PortaPack LCD_TE
|
||||
| boot_bit(sgpio_6, 1) // P2_2: SGPIO6, HOST_DATA6
|
||||
| (1 << 1) // P2_1: PortaPack ADDR
|
||||
| (1 << 0) // P2_0: PortaPack IO_STBX
|
||||
| (1 << 11) // P3_8: SPIFI_CS
|
||||
| (1 << 10) // P3_7: SPIFI_MOSI
|
||||
| (1 << 9) // P3_2: I2S0_RX_SDA
|
||||
| (1 << 8) // P3_1: I2S0_RX_WS
|
||||
| boot_bit(dfu_button, 0) // P2_8: 10K PD, BOOT2, DFU button
|
||||
| (1 << 4) // P2_4: PortaPack LCD_RDX
|
||||
| (0 << 3) // P2_3: PortaPack LCD_TE
|
||||
| boot_bit(sgpio_6, 1) // P2_2: SGPIO6, HOST_DATA6
|
||||
| (1 << 1) // P2_1: PortaPack ADDR
|
||||
| (1 << 0) // P2_0: PortaPack IO_STBX
|
||||
,
|
||||
.dir =
|
||||
#ifdef PRALINE
|
||||
(1 << 18) // P9_5: RFF5072 SCLK
|
||||
| boot_bit(trigger_out, 1) // P2_6: Trigger out
|
||||
| (0 << 14) // P4_10: FPGA CDONE
|
||||
| (1 << 15) // P6_7: 3V3 AUX_ENABLE
|
||||
| boot_bit(p1_ctrl1, 1) // P6_8: P1_CTRL1
|
||||
| boot_bit(sgpio_4, 0) // P9_4: FPGA SGPIO
|
||||
| (1 << 19) // PA_4: Output
|
||||
| (1 << 20) // PB_0: Output GND
|
||||
| (1 << 21) // PB_1: Output GND
|
||||
| (0 << 22) // PB_2: Unused
|
||||
| (1 << 23) // PB_3: Output
|
||||
| (0 << 24) // PB_4: Unused
|
||||
| (1 << 25) // PB_5: Output
|
||||
| (0 << 5) // P2_5: PPS (Bidirectional)
|
||||
| (1 << 12) // P4_8: Output
|
||||
| boot_bit(vregmode, 1) // P4_9: TPS62410 VREGMODE
|
||||
(1 << 18) // P9_5: RFF5072 SCLK
|
||||
| boot_bit(trigger_out, 1) // P2_6: Trigger out
|
||||
| (0 << 14) // P4_10: FPGA CDONE
|
||||
| boot_bit(aux_power_enable, 1) // P6_7: !3V3 AUX_ENABLE
|
||||
| boot_bit(p1_ctrl1, 1) // P6_8: P1_CTRL1
|
||||
| boot_bit(sgpio_4, 0) // P9_4: FPGA SGPIO
|
||||
| (1 << 19) // PA_4: Output
|
||||
| (1 << 20) // PB_0: Output GND
|
||||
| (1 << 21) // PB_1: Output GND
|
||||
| (0 << 22) // PB_2: Unused
|
||||
| (1 << 23) // PB_3: Output
|
||||
| (0 << 24) // PB_4: Unused
|
||||
| (1 << 25) // PB_5: Output
|
||||
| boot_bit(pps_in_out, 0) // P2_5: PPS (Bidirectional)
|
||||
| (1 << 12) // P4_8: Output
|
||||
| boot_bit(vregmode, 1) // P4_9: TPS62410 VREGMODE
|
||||
#else
|
||||
(0 << 18) // P9_5: HackRF CPLD.TDO(O)
|
||||
| (1 << 6) // P2_6: MIXER_SCLK
|
||||
| (0 << 14) // P4_10: SGPIO15, CPLD
|
||||
| (0 << 15) // P6_7: Varies by revision
|
||||
| (0 << 5) // P2_5: Varies by revision
|
||||
| (1 << 16) // P6_8: MIX_BYPASS
|
||||
| (0 << 13) // P4_9: SGPIO14, CPLD
|
||||
| (0 << 12) // P4_8: Varies by revision
|
||||
(0 << 18) // P9_5: HackRF CPLD.TDO(O)
|
||||
| (1 << 6) // P2_6: MIXER_SCLK
|
||||
| (0 << 14) // P4_10: SGPIO15, CPLD
|
||||
| boot_bit(rx_mix_bypass, 1) // P6_8: RX MIX BYPASS
|
||||
| (0 << 13) // P4_9: SGPIO14, CPLD
|
||||
| (0 << 12) // P4_8: Varies by revision
|
||||
#endif
|
||||
| (0 << 11) // P3_8: SPIFI_CS
|
||||
| (0 << 10) // P3_7: SPIFI_MOSI
|
||||
| (0 << 9) // P3_2: I2S0_RX_SDA
|
||||
| (0 << 8) // P3_1: I2S0_RX_WS
|
||||
| (0 << 7) // P2_8: BOOT2
|
||||
| (0 << 4) // P2_4: PortaPack LCD_RDX
|
||||
| (0 << 3) // P2_3: PortaPack LCD_TE
|
||||
| boot_bit(sgpio_6, 0) // P2_2: SGPIO6, HOST_DATA6
|
||||
| (0 << 1) // P2_1: PortaPack ADDR
|
||||
| (0 << 0) // P2_0: PortaPack IO_STBX
|
||||
| (0 << 11) // P3_8: SPIFI_CS
|
||||
| (0 << 10) // P3_7: SPIFI_MOSI
|
||||
| (0 << 9) // P3_2: I2S0_RX_SDA
|
||||
| (0 << 8) // P3_1: I2S0_RX_WS
|
||||
| boot_bit(dfu_button, 0) // P2_8: 10K PD, BOOT2, DFU button
|
||||
| (0 << 4) // P2_4: PortaPack LCD_RDX
|
||||
| (0 << 3) // P2_3: PortaPack LCD_TE
|
||||
| boot_bit(sgpio_6, 0) // P2_2: SGPIO6, HOST_DATA6
|
||||
| (0 << 1) // P2_1: PortaPack ADDR
|
||||
| (0 << 0) // P2_0: PortaPack IO_STBX
|
||||
},
|
||||
{
|
||||
// GPIO6
|
||||
@@ -449,16 +442,19 @@ const PALConfig pal_default_config = {
|
||||
|
||||
{map_vregmode.scu_port, map_vregmode.scu_pin, scu_config_normal_drive_t{.mode = map_vregmode.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // VREGMODE: TPS62410
|
||||
#ifdef PRALINE
|
||||
{map_VAA_en.scu_port, map_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_1: !VAA_EN
|
||||
{8, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_4: VBUS_IN_EN
|
||||
{8, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_5: VIN_IN_EN
|
||||
{map_en_1v2.scu_port, map_en_1v2.scu_pin, scu_config_normal_drive_t{.mode = map_en_1v2.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_7: EN_1V2
|
||||
{6, 7, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_7: 3.3V Aux Enable
|
||||
{4, 9, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_9: TPS62410 mode
|
||||
{map_p1_ctrl0.scu_port, map_p1_ctrl0.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl0.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_10: P1_CTRL0
|
||||
{map_p1_ctrl2.scu_port, map_p1_ctrl2.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl2.gpio_mode, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_9: P1_CTRL2 (Output VCC, PU ON,)
|
||||
{map_p2_ctrl0.scu_port, map_p2_ctrl0.scu_pin, scu_config_normal_drive_t{.mode = map_p2_ctrl0.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PE_3: P2_CTRL0
|
||||
{map_p2_ctrl1.scu_port, map_p2_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = map_p2_ctrl1.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PE_4: P2_CTRL1
|
||||
{map_VAA_en.scu_port, map_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_1: !VAA_EN
|
||||
{8, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_4: VBUS_IN_EN
|
||||
{8, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_5: VIN_IN_EN
|
||||
{map_en_1v2.scu_port, map_en_1v2.scu_pin, scu_config_normal_drive_t{.mode = map_en_1v2.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P8_7: EN_1V2
|
||||
{map_aux_power_enable.scu_port, map_aux_power_enable.scu_pin, scu_config_normal_drive_t{.mode = map_aux_power_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_7: !3.3V Aux Enable
|
||||
{map_aux_power_oc.scu_port, map_aux_power_oc.scu_pin, scu_config_normal_drive_t{.mode = map_aux_power_oc.gpio_mode, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P6_11: !3.3V Aux overcurrent input
|
||||
{4, 9, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_9: TPS62410 mode
|
||||
{map_p1_ctrl0.scu_port, map_p1_ctrl0.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl0.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_10: P1_CTRL0
|
||||
{map_p1_ctrl2.scu_port, map_p1_ctrl2.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl2.gpio_mode, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_9: P1_CTRL2 (Output VCC, PU ON,)
|
||||
{map_p2_ctrl0.scu_port, map_p2_ctrl0.scu_pin, scu_config_normal_drive_t{.mode = map_p2_ctrl0.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PE_3: P2_CTRL0
|
||||
{map_p2_ctrl1.scu_port, map_p2_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = map_p2_ctrl1.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PE_4: P2_CTRL1
|
||||
{map_ant_bias.scu_port, map_ant_bias.scu_pin, scu_config_normal_drive_t{.mode = map_ant_bias.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_12: !ANT BIAS
|
||||
{map_ant_bias_oc.scu_port, map_ant_bias_oc.scu_pin, scu_config_normal_drive_t{.mode = map_ant_bias_oc.gpio_mode, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P2_11: !ANT BIAS overcurrent input
|
||||
#endif
|
||||
|
||||
/* HackRF: I2C0 */
|
||||
@@ -502,28 +498,27 @@ const PALConfig pal_default_config = {
|
||||
{4, 10, scu_config_normal_drive_t{.mode = 7, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P4_10: FPGA Config Done (Input GND)
|
||||
{map_trigger_in.scu_port, map_trigger_in.scu_pin, scu_config_normal_drive_t{.mode = map_trigger_in.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // PD_12: TRIGGER IN (Input GND, Mode 4)
|
||||
{map_trigger_out.scu_port, map_trigger_out.scu_pin, scu_config_normal_drive_t{.mode = map_trigger_out.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P2_6: TRIGGER
|
||||
{2, 5, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}},
|
||||
{gpio_control::map_clkin_ctrl.scu_port, gpio_control::map_clkin_ctrl.scu_pin, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_20 CLKIN_ctrl
|
||||
{map_pps_in_out.scu_port, map_pps_in_out.scu_pin, scu_config_normal_drive_t{.mode = map_pps_in_out.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 1, .zif = 0}}, // P2_5 PPS bidirectional
|
||||
{map_clkin_ctrl.scu_port, map_clkin_ctrl.scu_pin, scu_config_normal_drive_t{.mode = map_clkin_ctrl.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_20 CLKIN_ctrl
|
||||
#else
|
||||
|
||||
{4, 9, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO14/BANK2F3M4: CPLD_P81
|
||||
{4, 10, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO15/BANK2F3M6: CPLD_P78
|
||||
{2, 6, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 1}}, // MIXER_SCLK/P31: 33pF, RFFC5072.SCLK(I)
|
||||
{4, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // RXENABLE
|
||||
{4, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // XCVR_EN: 10K PD
|
||||
{1, 20, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_20 CS_XCVR: MAX2837.CS(I)
|
||||
{4, 9, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO14/BANK2F3M4: CPLD_P81
|
||||
{4, 10, scu_config_normal_drive_t{.mode = 7, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // SGPIO15/BANK2F3M6: CPLD_P78
|
||||
{2, 6, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 1}}, // MIXER_SCLK/P31: 33pF, RFFC5072.SCLK(I)
|
||||
{4, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // RXENABLE
|
||||
{4, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // XCVR_EN: 10K PD
|
||||
{1, 20, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_20 CS_XCVR: MAX2837.CS(I)
|
||||
{map_hpf.scu_port, map_hpf.scu_pin, scu_config_normal_drive_t{.mode = map_hpf.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_0 HPF
|
||||
{map_rx_amp.scu_port, map_rx_amp.scu_pin, scu_config_normal_drive_t{.mode = map_rx_amp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_11 RX_AMP
|
||||
{map_rx_amp_pwr.scu_port, map_rx_amp_pwr.scu_pin, scu_config_normal_drive_t{.mode = map_rx_amp_pwr.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_12 !RX_AMP_PWR
|
||||
{map_tx_mix_bp.scu_port, map_tx_mix_bp.scu_pin, scu_config_normal_drive_t{.mode = map_tx_mix_bp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_2 TX_MIX_BP
|
||||
#endif
|
||||
|
||||
// RADIO & RF PATH (MAX2831, RFFC5072, Mixers, Switches, Amps)
|
||||
{1, 3, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P1_3 SSP1_MISO: MAX2837.DOUT(O)
|
||||
{1, 4, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_4 SSP1_MOSI: MAX2837.DIN(I)
|
||||
{1, 19, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // P1_19 SSP1_SCK: MAX2837.SCLK(I)
|
||||
{2, 11, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_11 RX_AMP
|
||||
{2, 12, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_12 !RX_AMP_PWR
|
||||
{4, 0, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_0 HP
|
||||
{5, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_1 LP
|
||||
{5, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_2 TX_MIX_BP
|
||||
|
||||
{1, 3, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P1_3 SSP1_MISO: MAX2837.DOUT(O)
|
||||
{1, 4, scu_config_normal_drive_t{.mode = 5, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_4 SSP1_MOSI: MAX2837.DIN(I)
|
||||
{1, 19, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // P1_19 SSP1_SCK: MAX2837.SCLK(I)
|
||||
{map_lpf.scu_port, map_lpf.scu_pin, scu_config_normal_drive_t{.mode = map_lpf.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_1 LPF
|
||||
#ifdef PRALINE
|
||||
{5, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_4: RFFC ENX
|
||||
{5, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_5: RFFC RESETX
|
||||
@@ -535,33 +530,31 @@ const PALConfig pal_default_config = {
|
||||
{13, 16, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PD_16: MAX5864 CS
|
||||
{14, 1, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PE_1: MAX2831 !SHDN
|
||||
{14, 2, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 1}}, // PE_2: MAX2831 RXTX
|
||||
{6, 3, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_3: MIX_ENABLE_N
|
||||
{map_p1_ctrl1.scu_port, map_p1_ctrl1.scu_pin, scu_config_normal_drive_t{.mode = map_p1_ctrl1.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 P1_CTRL1 (Output GND, Mode 4)
|
||||
{map_aa_en.scu_port, map_aa_en.scu_pin, scu_config_normal_drive_t{.mode = map_aa_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 1, .zif = 0}}, // P1_14: AA_EN
|
||||
{map_rf5072_mix_en.scu_port, map_rf5072_mix_en.scu_pin, scu_config_normal_drive_t{.mode = map_rf5072_mix_en.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_0: RF5072 MIX EN
|
||||
{9, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 0, .zif = 0}}, // P9_6: MAX2831 LD Input
|
||||
{6, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_5: TX enable
|
||||
{map_tx_enable.scu_port, map_tx_enable.scu_pin, scu_config_normal_drive_t{.mode = map_tx_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_5: TX enable
|
||||
{10, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_1: LPF enable
|
||||
{10, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 1, .ezi = 0, .zif = 0}}, // PA_2: RF amp enable
|
||||
{map_mix_bypass.scu_port, map_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_mix_bypass.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_3: MIX_ENABLE_N
|
||||
{map_rf_amp_enable.scu_port, map_rf_amp_enable.scu_pin, scu_config_normal_drive_t{.mode = map_rf_amp_enable.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // PA_2 RF_AMP_EN
|
||||
#else
|
||||
{5, 3, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_3 RX_MIX_BP
|
||||
{5, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_ENX
|
||||
{5, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_6 TX_AMP
|
||||
{5, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_7 CS_AD, PRALINE: RFFC5072 CS
|
||||
{5, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_RESETX
|
||||
{6, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // MIXER_SDATA
|
||||
{1, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // !MIX_BYPASS
|
||||
{2, 10, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // AMP_BYPASS
|
||||
{6, 8, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 MIX_BYPASS
|
||||
{6, 9, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // !TX_AMP_PWR
|
||||
{map_rx_mix_bp.scu_port, map_rx_mix_bp.scu_pin, scu_config_normal_drive_t{.mode = map_rx_mix_bp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_3 RX_MIX_BP
|
||||
{5, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_ENX
|
||||
{map_tx_amp.scu_port, map_tx_amp.scu_pin, scu_config_normal_drive_t{.mode = map_tx_amp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_6 TX_AMP
|
||||
{5, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P5_7 CS_AD, PRALINE: RFFC5072 CS
|
||||
{5, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // MIXER_RESETX
|
||||
{6, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // MIXER_SDATA
|
||||
{map_tx_mix_bypass.scu_port, map_tx_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_tx_mix_bypass.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_8 !TX MIX BYPASS
|
||||
{map_amp_bypass.scu_port, map_amp_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_amp_bypass.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_10 AMP_BYPASS
|
||||
{map_tx_amp_pwr.scu_port, map_tx_amp_pwr.scu_pin, scu_config_normal_drive_t{.mode = map_tx_amp_pwr.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // !TX_AMP_PWR
|
||||
{map_rx_mix_bypass.scu_port, map_rx_mix_bypass.scu_pin, scu_config_normal_drive_t{.mode = map_rx_mix_bypass.gpio_mode, .epd = 0, .epun = 0, .ehs = 1, .ezi = 0, .zif = 0}}, // P6_8 RX MIX BYPASS
|
||||
#endif
|
||||
|
||||
// SAFE TERMINATION (Unused pins grounded to prevent noise & save power)
|
||||
|
||||
#ifdef PRALINE
|
||||
{1, 1, scu_config_normal_drive_t{.mode = 0, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P1_1: Input GND
|
||||
{2, 7, scu_config_normal_drive_t{.mode = 0, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P2_7: Input GND
|
||||
{1, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P1_2: Input VCC
|
||||
{4, 6, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 0}}, // P4_6: Input VCC
|
||||
{6, 10, scu_config_normal_drive_t{.mode = 0, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P6_10: Output GND
|
||||
{4, 8, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_8: Output GND
|
||||
@@ -571,10 +564,6 @@ const PALConfig pal_default_config = {
|
||||
{11, 2, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // PB_2: Unused IN
|
||||
{11, 4, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // PB_4: Unused IN
|
||||
#else
|
||||
{1, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_1
|
||||
{1, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_2
|
||||
{2, 5, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_5
|
||||
{2, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_7
|
||||
{4, 8, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P4_8
|
||||
#endif
|
||||
|
||||
@@ -592,6 +581,12 @@ const PALConfig pal_default_config = {
|
||||
{6, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // CPLD_TCK: PortaPack CPLD.TCK(I)
|
||||
{6, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // CPLD_TDI: PortaPack CPLD.TDI(I)
|
||||
|
||||
{map_isp.scu_port, map_isp.scu_pin, scu_config_normal_drive_t{.mode = map_isp.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_7: ISP: 10K PU, Unused
|
||||
{map_dfu_boot_0.scu_port, map_dfu_boot_0.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_boot_0.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_1: 10K PU, BOOT0
|
||||
{map_dfu_boot_1.scu_port, map_dfu_boot_1.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_boot_1.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_2: 10K PD, BOOT1
|
||||
{map_dfu_button.scu_port, map_dfu_button.scu_pin, scu_config_normal_drive_t{.mode = map_dfu_button.gpio_mode, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, // P2_8: 10K PD, BOOT2, DFU button
|
||||
{map_lcd_wrx.scu_port, map_lcd_wrx.scu_pin, scu_config_normal_drive_t{.mode = map_lcd_wrx.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
|
||||
|
||||
}};
|
||||
|
||||
#ifndef PRALINE
|
||||
@@ -600,14 +595,8 @@ static const std::array<gpio_setup_t, 6> gpio_setup_og{{
|
||||
{
|
||||
|
||||
// GPIO0
|
||||
.data = (0 << 9) // P1_2: 10K PD, BOOT1
|
||||
| (1 << 8) // P1_1: 10K PU, BOOT0
|
||||
| (1 << 7) // P2_7: 10K PU, ISP
|
||||
,
|
||||
.dir = (0 << 9) // P1_2: 10K PD, BOOT1
|
||||
| (0 << 8) // P1_1: 10K PU, BOOT0
|
||||
| (0 << 7) // P2_7: 10K PU, ISP
|
||||
},
|
||||
.data = 0,
|
||||
.dir = 0},
|
||||
{// GPIO1
|
||||
.data = 0,
|
||||
.dir = 0},
|
||||
@@ -630,13 +619,13 @@ static const std::array<gpio_setup_t, 6> gpio_setup_og{{
|
||||
.dir = 0},
|
||||
{
|
||||
// GPIO5
|
||||
.data = (0 << 15) // P6_7: TX
|
||||
.data = boot_bit(og_tx, 0) // P6_7: TX
|
||||
| boot_bit(sgpio_13, 0) // P4_8: SGPIO13, HOST_SYNC_EN
|
||||
| (1 << 5) // P2_5: RX
|
||||
| boot_bit(og_rx, 1) // P2_5: RX
|
||||
,
|
||||
.dir = (1 << 15) // P6_7: TX
|
||||
.dir = boot_bit(og_tx, 1) // P6_7: TX
|
||||
| boot_bit(sgpio_13, 0) // P4_8: SGPIO13, HOST_SYNC_EN
|
||||
| (1 << 5) // P2_5: RX
|
||||
| boot_bit(og_rx, 1) // P2_5: RX
|
||||
},
|
||||
|
||||
}};
|
||||
@@ -645,24 +634,24 @@ static const std::array<gpio_setup_t, 6> gpio_setup_og{{
|
||||
static const std::array<gpio_setup_t, 6> gpio_setup_r9{{
|
||||
{
|
||||
// GPIO0
|
||||
.data = (0 << 9) // P1_2: 10K PD, BOOT1, CLKOUT_EN
|
||||
| (1 << 8) // P1_1: 10K PU, BOOT0, MCU_CLK_EN
|
||||
| (1 << 7) // P2_7: 10K PU, ISP, RX
|
||||
.data = boot_bit(r9_clkout_en, 0) // P1_2: 10K PD, BOOT1, CLKOUT_EN
|
||||
| boot_bit(r9_mcu_clk_en, 1) // P1_1: 10K PU, BOOT0, MCU_CLK_EN
|
||||
| boot_bit(r9_rx, 1) // P2_7: 10K PU, ISP, RX
|
||||
,
|
||||
.dir = (0 << 9) // P1_2: 10K PD, BOOT1, CLKOUT_EN
|
||||
| (0 << 8) // P1_1: 10K PU, BOOT0, MCU_CLK_EN
|
||||
| (0 << 7) // P2_7: 10K PU, ISP, RX
|
||||
.dir = boot_bit(r9_clkout_en, 1) // P1_2: 10K PD, BOOT1, CLKOUT_EN
|
||||
| boot_bit(r9_mcu_clk_en, 1) // P1_1: 10K PU, BOOT0, MCU_CLK_EN
|
||||
| boot_bit(r9_rx, 1) // P2_7: 10K PU, ISP, RX
|
||||
},
|
||||
{// GPIO1
|
||||
.data = 0,
|
||||
.dir = 0},
|
||||
{
|
||||
// GPIO2
|
||||
.data = boot_bit(r9_1v8_en, 0) // P5_0: EN1V8, 10K PD
|
||||
| (1 << 4) // P4_4: !ANT_BIAS
|
||||
.data = boot_bit(r9_1v8_en, 0) // P5_0: EN1V8, 10K PD
|
||||
| boot_bit(ant_bias, 1) // P4_4: !ANT_BIAS
|
||||
,
|
||||
.dir = boot_bit(r9_1v8_en, 1) // P5_0: EN1V8, 10K PD
|
||||
| (1 << 4) // P4_4: !ANT_BIAS
|
||||
.dir = boot_bit(r9_1v8_en, 1) // P5_0: EN1V8, 10K PD
|
||||
| boot_bit(ant_bias, 1) // P4_4: !ANT_BIAS
|
||||
},
|
||||
{
|
||||
// GPIO3
|
||||
@@ -675,54 +664,49 @@ static const std::array<gpio_setup_t, 6> gpio_setup_r9{{
|
||||
.dir = 0},
|
||||
{
|
||||
// GPIO5
|
||||
.data = (0 << 15) // P6_7: CLKIN_EN
|
||||
| (0 << 12) // P4_8: CLKIN_DETECT
|
||||
| (0 << 5) // P2_5: HOST_SYNC_EN
|
||||
.data = boot_bit(r9_clkin_en, 0) // P6_7: CLKIN_EN
|
||||
| (0 << 12) // P4_8: CLKIN_DETECT
|
||||
| (0 << 5) // P2_5: HOST_SYNC_EN
|
||||
,
|
||||
.dir = (1 << 15) // P6_7: CLKIN_EN
|
||||
| (0 << 12) // P4_8: CLKIN_DETECT
|
||||
| (0 << 5) // P2_5: HOST_SYNC_EN
|
||||
.dir = boot_bit(r9_clkin_en, 1) // P6_7: CLKIN_EN
|
||||
| (0 << 12) // P4_8: CLKIN_DETECT
|
||||
| (0 << 5) // P2_5: HOST_SYNC_EN
|
||||
},
|
||||
}};
|
||||
|
||||
/* Additional SCU configuration for HackRF OG */
|
||||
static const std::array<scu_setup_t, 9> pins_setup_og{{
|
||||
static const std::array<scu_setup_t, 7> pins_setup_og{{
|
||||
|
||||
/* Power control */
|
||||
{map_og_VAA_en.scu_port, map_og_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_og_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* !VAA_ENABLE: 10K PU, Q3.G(I), power to VAA */
|
||||
{map_og_1v8_en.scu_port, map_og_1v8_en.scu_pin, scu_config_normal_drive_t{.mode = map_og_1v8_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* EN1V8/P70: 10K PD, TPS62410.EN2(I), 1V8LED.A(I) */
|
||||
|
||||
/* Radio section control */
|
||||
{2, 5, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* RX/P43: U7.VCTL1(I), U10.VCTL1(I), U2.VCTL1(I) */
|
||||
{4, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* TXENABLE/P55: MAX2837.TXENABLE(I) */
|
||||
{6, 7, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* TX/P42: U7.VCTL2(I), U10.VCTL2(I), U2.VCTL2(I) */
|
||||
|
||||
{2, 5, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* RX/P43: U7.VCTL1(I), U10.VCTL1(I), U2.VCTL1(I) */
|
||||
{4, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* TXENABLE/P55: MAX2837.TXENABLE(I) */
|
||||
{map_og_tx.scu_port, map_og_tx.scu_pin, scu_config_normal_drive_t{.mode = map_og_tx.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* TX/P42: U7.VCTL2(I), U10.VCTL2(I), U2.VCTL2(I) */
|
||||
{map_og_rx.scu_port, map_og_rx.scu_pin, scu_config_normal_drive_t{.mode = map_og_rx.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P2_5
|
||||
/* SGPIO for sample transfer interface to HackRF CPLD. */
|
||||
{map_sgpio_13.scu_port, map_sgpio_13.scu_pin, scu_config_normal_drive_t{.mode = map_sgpio_13.gpio_mode, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* SGPIO13/BANK2F3M2: CPLD.90/HOST_SYNC_EN(I) */
|
||||
/* Miscellaneous */
|
||||
{1, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* P1_1/P74: 10K PU, BOOT0 */
|
||||
{1, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* P1_2/P73: 10K PD, BOOT1 */
|
||||
{2, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* ISP: 10K PU, Unused */
|
||||
|
||||
}};
|
||||
|
||||
/* Additional SCU configuration for HackRF r9 */
|
||||
static const std::array<scu_setup_t, 9> pins_setup_r9{{
|
||||
/* Power control */
|
||||
{map_r9_VAA_en.scu_port, map_r9_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* !VAA_ENABLE: 10K PU, Q3.G(I), power to VAA */
|
||||
{map_r9_1v8_en.scu_port, map_r9_1v8_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_1v8_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* EN1V8: 10K PD, TPS62410.EN2(I), 1V8LED.A(I) */
|
||||
{map_r9_VAA_en.scu_port, map_r9_VAA_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_VAA_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // !VAA_ENABLE: 10K PU, Q3.G(I), power to VAA
|
||||
{map_r9_1v8_en.scu_port, map_r9_1v8_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_1v8_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // EN1V8: 10K PD, TPS62410.EN2(I), 1V8LED.A(I)
|
||||
|
||||
/* Radio section control */
|
||||
{2, 7, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* RX/ISP/P96: U7.VCTL(I), U10.VCTL(I), U2.VCTL(I) */
|
||||
{4, 4, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* !ANT_BIAS: 10K PU, Q4.G(I) */
|
||||
{map_r9_rx.scu_port, map_r9_rx.scu_pin, scu_config_normal_drive_t{.mode = map_r9_rx.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // RX/ISP/P96: U7.VCTL(I), U10.VCTL(I), U2.VCTL(I)
|
||||
{map_ant_bias.scu_port, map_ant_bias.scu_pin, scu_config_normal_drive_t{.mode = map_ant_bias.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // !ANT_BIAS: 10K PU, Q4.G(I)
|
||||
|
||||
/* SGPIO for sample transfer interface to HackRF CPLD. */
|
||||
{2, 5, scu_config_normal_drive_t{.mode = 4, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* BANK2F3M2: CPLD.90/HOST_SYNC_EN(I) */
|
||||
|
||||
/* Clock control */
|
||||
{1, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* MCU_CLK_EN/BOOT0: 10K PU, U28.1A(I) */
|
||||
{1, 2, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* CLKOUT_EN/BOOT1: 10K PD, U28.2A(I) */
|
||||
{6, 7, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* CLKIN_EN: U16.SEL(I), U26.1A(I) */
|
||||
{map_r9_mcu_clk_en.scu_port, map_r9_mcu_clk_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_mcu_clk_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_1: MCU_CLK_EN/BOOT0: 10K PU, U28.1A(I)
|
||||
{map_r9_clkout_en.scu_port, map_r9_clkout_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_clkout_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, // P1_2: CLKOUT_EN/BOOT1: 10K PD, U28.2A(I)
|
||||
{map_r9_clkin_en.scu_port, map_r9_clkin_en.scu_pin, scu_config_normal_drive_t{.mode = map_r9_clkin_en.gpio_mode, .epd = 0, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* CLKIN_EN: U16.SEL(I), U26.1A(I) */
|
||||
|
||||
/* Miscellaneous */
|
||||
{4, 8, scu_config_normal_drive_t{.mode = 1, .epd = 1, .epun = 1, .ehs = 0, .ezi = 0, .zif = 0}}, /* CLKIN_DETECT: U26.2Y(O) */
|
||||
@@ -733,13 +717,11 @@ static const std::array<scu_setup_t, 9> pins_setup_r9{{
|
||||
|
||||
#ifdef PRALINE
|
||||
|
||||
static const std::array<scu_setup_t, 43> pins_setup_portapack{{
|
||||
static const std::array<scu_setup_t, 41> pins_setup_portapack{{
|
||||
{2, 0, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* U0_TXD: PortaPack P2_0/IO_STBX */
|
||||
{2, 1, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* U0_RXD: PortaPack P2_1/ADDR */
|
||||
{2, 3, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 1}}, /* I2C1_SDA: PortaPack P2_3/LCD_TE */
|
||||
{2, 4, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 1}}, /* I2C1_SCL: PortaPack P2_4/LCD_RDX */
|
||||
{2, 8, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, /* P2_8: 10K PD, BOOT2, DFU switch, PortaPack P2_8/<unused> */
|
||||
{2, 9, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* P2_9: 10K PD, BOOT3, PortaPack P2_9/LCD_WRX */
|
||||
{2, 13, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* P2_13: PortaPack P2_13/DIR */
|
||||
{7, 0, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* GPIO3_8: PortaPack GPIO3_8(IO) */
|
||||
{7, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* GPIO3_9: PortaPack GPIO3_9(IO) */
|
||||
@@ -790,13 +772,11 @@ static const std::array<scu_setup_t, 43> pins_setup_portapack{{
|
||||
}};
|
||||
|
||||
#else
|
||||
static const std::array<scu_setup_t, 26> pins_setup_portapack{{
|
||||
static const std::array<scu_setup_t, 24> pins_setup_portapack{{
|
||||
{2, 0, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* U0_TXD: PortaPack P2_0/IO_STBX */
|
||||
{2, 1, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* U0_RXD: PortaPack P2_1/ADDR */
|
||||
{2, 3, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* I2C1_SDA: PortaPack P2_3/LCD_TE */
|
||||
{2, 4, scu_config_normal_drive_t{.mode = 4, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* I2C1_SCL: PortaPack P2_4/LCD_RDX */
|
||||
{2, 8, scu_config_normal_drive_t{.mode = 1, .epd = 0, .epun = 0, .ehs = 0, .ezi = 1, .zif = 1}}, /* P2_8: 10K PD, BOOT2, DFU switch, PortaPack P2_8/<unused> */
|
||||
{2, 9, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* P2_9: 10K PD, BOOT3, PortaPack P2_9/LCD_WRX */
|
||||
{2, 13, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* P2_13: PortaPack P2_13/DIR */
|
||||
{7, 0, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* GPIO3_8: PortaPack GPIO3_8(IO) */
|
||||
{7, 1, scu_config_normal_drive_t{.mode = 0, .epd = 0, .epun = 1, .ehs = 0, .ezi = 1, .zif = 0}}, /* GPIO3_9: PortaPack GPIO3_9(IO) */
|
||||
@@ -1075,4 +1055,4 @@ extern "C" void _default_exit(void) {
|
||||
| (1U << 26) // SPI_RST
|
||||
| (1U << 28) // ADCHS_RST
|
||||
;
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user